THREE DIMENSIONAL CAPACITOR
Integrated capacitor structures and methods for fabricating same are provided. In an embodiment, the integrated capacitor structures exploit the capacitance that can be formed in a plane that is perpendicular to that of the substrate, resulting in three-dimensional capacitor structures. This allows for integrated capacitor structures with higher capacitance to be formed over relatively small substrate areas. Embodiments are suitable for use by charge pumps and can be fabricated to have more or less capacitance as desired by the application.
1 . A capacitor structure, comprising:
a substrate;
a first conductor disposed over the substrate, the first conductor having a top surface, a first sidewall, and a second sidewall;
a dielectric layer disposed over the first conductor, the dielectric layer covering the first sidewall and the second sidewall of the first conductor; and
a second conductor disposed over the dielectric layer, the second conductor having a first portion disposed along the first sidewall of the first conductor and a second portion disposed along the second sidewall of the first conductor.
2 . The capacitor structure of claim 1 , wherein a first capacitance is formed between the first sidewall of the first conductor and the first portion of the second conductor, and a second capacitance is formed between the second sidewall of the first conductor and the second portion of the second conductor.
3 . The capacitor structure of claim 1 , wherein the dielectric layer further covers the top surface of the first conductor, and wherein the second conductor comprises a third portion disposed over the top surface of the first conductor.
4 . The capacitor structure of claim 3 , wherein a capacitance is formed between the top surface of the first conductor and the third portion of the second conductor.
5 . The capacitor structure of claim 3 , wherein the second conductor further comprises a fourth portion disposed laterally to the first conductor and adjacent to the first portion.
6 . The capacitor structure of claim 5 , wherein a capacitance is formed between the substrate and the fourth portion of the second conductor.
7 . The capacitor structure of claim 1 , wherein the dielectric layer comprises an oxide-nitride-oxide (ONO) layer.
8 . The capacitor structure of claim 1 , wherein the first conductor is disposed directly over the substrate.
9 . The capacitor structure of claim 1 , further comprising:
an isolation layer disposed over the substrate, wherein the first conductor is disposed over the isolation layer.
10 . The capacitor structure of claim 1 , wherein at least one of the first conductor and the second conductor comprises a polycrystalline silicon.
11 . A capacitor structure, comprising:
a substrate;
a first conductor layer disposed over the substrate, the first conductor layer patterned to form first and second conductors spaced by a separation region, the first and second conductors each having a top surface, a first sidewall, and a second sidewall;
a dielectric layer disposed over the first and second sidewalls of each of the first and second conductors; and
a second conductor layer disposed over the dielectric layer, the second conductor layer having a first portion disposed along the first sidewall of the first conductor, a second portion disposed along the first sidewall of the second conductor, and a third portion disposed in the separation region between the second sidewall of the first conductor and the second sidewall of the second conductor.
12 . The capacitor structure of claim 11 , wherein a height of the second conductor layer is greater than a half length of the separation region.
13 . The capacitor structure of claim 11 , wherein the third portion of the second conductor layer bridges the separation region between the first and second conductors.
14 . The capacitor structure of claim 11 , wherein the third portion of the second conductor layer includes a pinch off region.
15 . The capacitor structure of claim 11 , wherein the dielectric layer is further disposed over the top surfaces of the first and second conductors, and wherein the second conductor layer further comprises a fourth portion disposed over the top surfaces of the first and second conductors.
16 . A method of fabricating a capacitor structure, comprising:
disposing a first conductor layer over a substrate;
patterning the first conductor layer to form first and second conductors spaced by a separation region, the first and second conductors each having a top surface, a first sidewall, and a second sidewall;
disposing a dielectric layer over the first and second conductors and the substrate; and
disposing a second conductor layer over the dielectric layer.
17 . The method of claim 16 , further comprising:
etching the second conductor layer along the top surfaces of the first and second conductors.
18 . The method of claim 17 , further comprising:
etching the second conductor layer in a portion of the separation region to form a first spacer of the second conductor layer along the first sidewall of the first conductor and a second spacer of the second conductor layer along the first sidewall of the second conductor.
19 . The method of claim 16 , further comprising:
disposing an isolation layer over the substrate, wherein the first conductor layer is disposed over the isolation layer.
20 . The method of claim 16 , wherein disposing the dielectric layer comprises:
disposing a first oxide layer over the first conductor layer;
disposing a nitride layer over the first oxide layer; and
disposing a second oxide layer over the nitride layer.