Charge Trapping Split Gate Embedded Flash Memory and Associated Methods
Semiconductor devices and methods of manufacturing such devices are described herein. According to embodiments, the semiconductor device can be made by forming an dielectric layer at a first region and at a second region of a semiconductor substrate. A gate conductor layer is disposed over the dielectric formed in the first and the second regions of the semiconductor substrate, and the second region is masked. A split gate memory cell is formed in the first region of the semiconductor substrate with a first gate length. The first region is then masked, and the second region is etched to define a logic gate that has a second gate length. The first and second gate lengths can be different.
1 - 10 . (canceled)
11 . A semiconductor device, comprising:
a split gate memory cell, having a first gate length, formed at a first region of a semiconductor substrate over a first dielectric layer; and
a logic gate, having a second gate length, formed in a second region of the semiconductor substrate over a second dielectric layer,
wherein the first gate length is different from the second gate length, and
wherein the first region comprises a core region and the second region comprises a periphery region and wherein the first dielectric layer is thicker than the second dielectric layer.
12 . The semiconductor device of claim 11 , wherein the first gate length is greater than the second gate length.
13 . (canceled)
14 . The device of claim 11 , further comprising a second logic gate, having a third gate length, formed in a third region of the semiconductor substrate.
15 . The device of claim 14 , further comprising a third gate dielectric layer formed in the third region, wherein the third gate dielectric is thicker than the first logic gate dielectric.
16 . The device of claim 14 , wherein the third gate length is greater than one of the first and the second gate lengths.
17 . The device of claim 11 , wherein the split gate memory cell comprises:
a select gate;
a charge trapping dielectric disposed over the select gate; and
a memory gate disposed over the charge trapping layer and adjacent to the select gate.
18 . The device of claim 17 , wherein the select gate is formed from a first gate conductor layer and the memory gate is formed from a second gate conductor layer.
19 . The device of claim 17 , wherein the charge trapping dielectric comprises a nitride layer and a dielectric layer.
20 . The device of claim 19 , wherein the nitride layer comprises silicon rich nitride.
21 . The device of claim 11 , wherein each of the first and second gate lengths correspond to technology nodes chosen from one of: 33'nm, 25X nm, 23X nm, 17X nm, 13X nm, 11X nm, 9X nm, 6X nm, 5X nm, 4X nm, 3X nm, 2X nm, and 1X nm.
22 . The device of claim 11 , wherein the first get length corresponds to a first technology node and the second gate length corresponds to a second technology node.
23 . The device of claim 14 , wherein the first gate length is greater than the third gate length.
24 . The device of claim 14 , wherein the first gate length is greater than the second gate length and the third gate length.