Semiconductor device and method of forming the same
View Patent ↗A semiconductor device includes a semiconductor substrate having first and second regions, a first pillar transistor, and a second pillar transistor, wherein the first pillar transistor comprises a first semiconductor pillar disposed in the first region, and a first gate electrode covering a side surface of the first semiconductor pillar, wherein the second pillar transistor comprises a second semiconductor pillar disposed in the second region, and a second gate electrode covering a side surface of the second semiconductor pillar, wherein the first gate electrode is different in height from the second gate electrode, and the first and second pillar transistors form a CMOS device.
1. A semiconductor device comprising:
a semiconductor substrate having first and second regions;
a first pillar transistor; and
a second pillar transistor,
wherein the first pillar transistor comprises a first semiconductor pillar disposed in the first region, and a first gate electrode covering a side surface of the first semiconductor pillar,
wherein the second pillar transistor comprises a second semiconductor pillar disposed in the second region, and a second gate electrode covering a side surface of the second semiconductor pillar,
wherein the first gate electrode is different in height from the second gate electrode, and
the first and second pillar transistors form a CMOS device.
2. The semiconductor device according to claim 1 , wherein the first gate electrode is lower in height from the second gate electrode.
3. The semiconductor device according to claim 2 , wherein the first pillar transistor is an n-channel MOS transistor, and the second pillar transistor is a p-channel MOS transistor.
4. The semiconductor device according to claim 3 , wherein the first semiconductor pillar comprises a p-type semiconductor, and the second semiconductor pillar comprises an n-type semiconductor.
5. The semiconductor device according to claim 3 , wherein the first gate electrode comprises an n-type semiconductor, and the second gate electrode comprises a p-type semiconductor.
6. The semiconductor device according to claim 4 , further comprising:
a first top diffusion layer of an n-type semiconductor disposed over the first semiconductor pillar;
a first bottom diffusion layer of an n-type semiconductor disposed under the first semiconductor pillar;
a second top diffusion layer of a p-type semiconductor disposed over the second semiconductor pillar; and
a second bottom diffusion layer of a p-type semiconductor disposed under the second semiconductor pillar.
7. The semiconductor device according to claim 1 , wherein the first region comprises a p-well region, and the second region comprises an n-well region.
8. The semiconductor device according to claim 1 , further comprising:
a first gate insulator disposed between the first semiconductor pillar and the first gate electrode; and
a second gate insulator disposed between the second semiconductor pillar and the second gate electrode.
9. A semiconductor device comprising:
a semiconductor substrate having first and second regions;
a first pillar transistor; and
a second pillar transistor,
wherein the first pillar transistor comprises a first semiconductor pillar disposed in the first region, and a first gate electrode covering a side surface of the first semiconductor pillar, the first gate electrode having a first gate length,
wherein the second pillar transistor comprises a second semiconductor pillar disposed in the second region, and a second gate electrode covering a side surface of the second semiconductor pillar, the second gate electrode having a second gate length,
wherein the first gate length is different in height from the second gate length, and
the first and second pillar transistors form a CMOS device.
10. The semiconductor device according to claim 9 , wherein the first gate length is shorter in height from the second gate length.
11. The semiconductor device according to claim 10 , wherein the first pillar transistor is an n-channel MOS transistor, and the second pillar transistor is a p-channel MOS transistor.
12. The semiconductor device according to claim 11 , wherein the first semiconductor pillar comprises a p-type semiconductor, and the second semiconductor pillar comprises an n-type semiconductor.
13. The semiconductor device according to claim 11 , wherein the first gate electrode comprises an n-type semiconductor, and the second gate electrode comprises a p-type semiconductor.
14. The semiconductor device according to claim 12 , further comprising:
a first top diffusion layer of an n-type semiconductor disposed over the first semiconductor pillar;
a first bottom diffusion layer of an n-type semiconductor disposed under the first semiconductor pillar;
a second top diffusion layer of a p-type semiconductor disposed over the second semiconductor pillar; and
a second bottom diffusion layer of a p-type semiconductor disposed under the second semiconductor pillar.
15. The semiconductor device according to claim 9 , wherein the first region comprises a p-well region, and the second region comprises an n-well region.
16. The semiconductor device according to claim 9 , further comprising:
a first gate insulator disposed between the first semiconductor pillar and the first gate electrode; and
a second gate insulator disposed between the second semiconductor pillar and the second gate electrode.