Memory gate landing pad made from dummy features
View Patent ↗Embodiments described herein generally relate to landing gate pads for contacts and manufacturing methods therefor. A bridge is formed between two features to allow a contact to be disposed, at least partially, on the bridge. Landing the contact on the bridge avoids additional manufacturing steps to create a target for a contact.
1. A semiconductor device, comprising:
a substrate;
a first memory cell gate disposed on the substrate;
a dummy feature disposed on the substrate;
a counterpart memory cell gate disposed on the substrate, wherein the counterpart memory cell gate is located between the first memory cell gate and the dummy feature so as to form a bridge portion that is below opposing edges of the first memory cell gate and the dummy feature; and
a contact at least partially disposed on the bridge portion and at least partially disposed on the dummy feature,
wherein the counterpart memory cell gate is a memory gate disposed over a charge trapping dielectric.
2. The semiconductor device of claim 1 , further comprising a dielectric disposed underneath the dummy feature.
3. The semiconductor device of claim 1 , wherein the dummy feature is electrically isolated from the first memory cell gate.
4. The semiconductor device of claim 1 , wherein a top surface of the dummy feature is up to about twice as long as a contact surface of the contact.
5. The semiconductor device of claim 1 , wherein a location of the contact is between the dummy feature and at least one of the first memory cell gate and a second dummy feature.
6. The semiconductor device of claim 1 , wherein a top surface of the dummy feature is up to twice as long as a contact surface of the contact.
7. The semiconductor device of claim 1 , wherein the dummy feature is a peninsula.
8. The semiconductor device of claim 1 , wherein the contact is also at least partially disposed on a second bridge portion.
9. The semiconductor device of claim 1 , wherein the counterpart memory cell gate is adjacent to the first memory cell gate and the dummy feature.
10. A method of fabricating a semiconductor device, comprising:
disposing a gate layer on a substrate;
forming a plurality of features in the gate layer including a memory cell gate and at least one dummy feature;
disposing an insulator over the plurality of features;
disposing a further gate layer on the plurality of features;
removing a portion of the further gate layer to form a counterpart memory cell gate between the memory cell gate and the one dummy feature, wherein a distance between the memory cell gate and the one dummy feature is less than a bridging distance so as to form a recess portion in the counterpart memory cell gate; and
forming a contact on at least the recess portion of the counterpart memory cell gate and at least a portion of the dummy feature,
wherein the counterpart memory cell gate is a memory gate disposed over a charge trapping dielectric.
11. The method of fabricating a semiconductor of claim 10 , further comprising disposing a dielectric on the substrate before forming the dummy feature, wherein forming the dummy feature leaves the dummy feature on a thick dielectric.
12. The method of fabricating a semiconductor of claim 10 , further comprising electrically isolating the dummy feature from the counterpart memory cell gate.
13. The method of fabricating a semiconductor of claim 10 , wherein a top surface of the dummy feature is formed to be up to twice as long as a contact surface of the contact.
14. The method of fabricating a semiconductor of claim 10 , wherein a location of the contact is between the dummy feature and a second dummy feature.
15. The method of fabricating a semiconductor of claim 10 , wherein forming the contact further comprises forming the contact over a second recess portion.