IP Library Granted Patent US 8,921,216
Granted Patent B2
US 8,921,216 · App. 13/717,062 · Granted Dec 30, 2014

Semiconductor device and method of fabricating the same

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Quick Facts
Patent No.
US 8,921,216
App. No.
13/717,062
Granted
Dec 30, 2014
Kind
B2
Abstract

A method for fabricating a semiconductor device includes defining a curved active region by forming a plurality of trenches over a semiconductor substrate, forming an insulating layer to fill the plurality of trenches, and forming a pair of gate lines crossing the curved active region, so that it is possible to prevent leaning of an active region by forming a curved active region.

Claims (31)

1. A method of fabricating a semiconductor device, comprising:

defining a curved active region by forming a plurality of trenches over a semiconductor substrate;

forming an insulating layer to fill the plurality of trenches; and

forming a pair of gate lines crossing the curved active region,

wherein the curved active region includes a first region which protrudes toward a first direction and a second region which is in contact with the first region and protrudes toward a second direction crossing the first direction, and

wherein one of the pair of gate lines crosses the first region, the other of the pair of gate lines crosses the second region, and the pair of gate lines extend along a third direction crossing the first and second directions.

2. The method of claim 1 , wherein the defining of the curved active region comprises:

forming a first trench having a major axis and a minor axis by etching the semiconductor substrate; and

forming a second trench by etching the semiconductor substrate such that the second trench is coupled to adjacent first trenches in the minor axis direction of the first trench.

3. The method of claim 1 , wherein the pair of gate lines are spaced with a gap in parallel with each other.

4. The method of claim 1 , further comprising:

forming a bit line that is in contact with the curved active region and extends to intersect the pair of gate lines.

5. The method of claim 1 , wherein the curved active region has an internal angle of 1° to 179°.

6. The method of claim 1 , wherein the curved active region includes at least one curve.

7. The method of claim 1 , wherein the gate line includes a buried gate line.

8. A method of fabricating a semiconductor device, comprising:

forming a first trench having a major axis and a minor axis over a semiconductor substrate;

forming a first insulating layer to fill the first trench;

forming a second trench connecting adjacent first trenches in the minor axis direction by etching the semiconductor substrate;

defining a curved active area defined by the first and second trenches by filling the second trench with a second insulating layer; and

forming a pair of gate lines crossing the curved active region.

9. The method of claim 8 , wherein the pair of gate lines are spaced with a gap in parallel with each other.

10. The method of claim 8 , further comprising:

forming a bit line that is in contact with the curved active region and extends to intersect the pair of gate lines.

11. The method of claim 8 , wherein the curved active region has an internal angle of 1° to 179°.

12. A method of fabricating a semiconductor device, comprising:

forming first trenches over a semiconductor substrate; and

forming second trenches over the semiconductor substrate, wherein curved active regions are defined by using the first and second trenches.

13. The method of claim 12 , further comprising:

forming an insulating layer to fill the first and second trenches; and

forming a pair of gate lines crossing one of the curved active regions.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 7, 2024
From: SK HYNIX INC.
To: MIMIRIP LLC
Reel/Frame 067335/0246 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 17, 2012
From: LEE, HYO-SEOK; YEOM, SEUNG-JIN; LIM, SUNG-WON
To: SK HYNIX INC.
Reel/Frame 029485/0742 →