Semiconductor integrated circuit having differential signal transmission structure and method for driving the same

1. A semiconductor integrated circuit, comprising:

an input data line pair;

a sense amplifier configured to sense and amplify data loaded on the input data line pair and output the amplified data to an output data line pair, in response to a control signal; and

a sense amplification controller configured to detect an amplification level on the output data line pair, and output the control signal for controlling the sense amplifier based on a sense amplification enable signal and the detected amplification level,

wherein the sense amplification controller comprises:

a reset unit configured to receive the sense amplification enable signal and reset a first input node of an output unit in response to the sense amplification enable signal;

a sensing driving unit configured to sense voltage levels of the output data line pair and drive the first input node of the output unit to a predetermined voltage level; and

the output unit configured to output the control signal in response to the sense amplification enable signal provided to a second input node and a voltage on the first input node, and provide the control signal to the sense amplifier.

2. The semiconductor integrated circuit of claim 1 , wherein the sense amplification enable signal is activated during a predetermined period in response to a command.

3. The semiconductor integrated circuit of claim 1 , wherein the reset unit comprises an NMOS transistor having a source coupled to a ground voltage terminal, a drain coupled to the first input node, and a gate to receive an inverted sense amplification enable signal.

4. The semiconductor integrated circuit of claim 1 , wherein the sensing driving unit comprises:

a first PMOS transistor having a source coupled to a power supply voltage terminal, a drain coupled to the first input node, and a gate coupled to one of the output data line pair; and

a second PMOS transistor having a source coupled to the power supply voltage terminal, a drain coupled to the first input node, and a gate coupled to the other of the output data line pair.

5. The semiconductor integrated circuit of claim 1 , wherein the output unit comprises a NOR gate configured to output the control signal based on the sense amplification enable signal and the voltage of the first input node.

6. The semiconductor integrated circuit of claim 1 , wherein the control signal is configured to limit an activation period of the sense amplification enable signal to thereby deactivate the sense amplifier, if the detected amplification level reaches a predetermined voltage level.

7. The semiconductor integrated circuit of claim 6 , wherein the predetermined voltage level corresponds to a minimum voltage difference of the output data line pair that is capable of being sensed by an amplifier at a rear stage of the sense amplifier.

8. A semiconductor integrated circuit, comprising:

a memory cell;

a bit line sense amplifier (BLSA) configured to sense and amplify data of the memory cell, loaded on a bit line pair;

a local sense amplifier (LSA) configured to sense and amplify an output signal of the bit line sense amplifier, loaded on a first local data line pair, and output a first amplified signal to a second local data line pair, in response to a control signal;

a global sense amplifier (IOSA) configured to sense and amplify the signal loaded on the second local data line pair and output a second amplified signal to a global data line; and

an LSA controller configured to detect a voltage level of the first amplified signal, and output the control signal for controlling the LSA based on a LSA enable signal and the detected voltage level,

wherein the LSA controller comprises:

a reset unit configured to reset a first input node of an output unit in response to the LSA enable signal;

a sensing driving unit configured to sense the voltage level of the first amplified signal and drive the first input node of the output unit to a predetermined voltage level; and

the output unit configured to output the control signal in response to the LSA enable signal provided to a second input node and a voltage level of the first input node, and provide the control signal to the LSA.

9. The semiconductor integrated circuit of claim 8 , wherein the LSA enable signal is activated during a predetermined period in response to a read command.

10. The semiconductor integrated circuit of claim 8 , wherein the reset unit comprises an MOS transistor having a source coupled to a ground voltage terminal, a drain coupled to the first input node, and a gate to receive an inverted LSA enable signal.

11. The semiconductor integrated circuit of claim 8 , wherein the sensing driving unit comprises:

a first PMOS transistor having a source coupled to a core voltage terminal, a drain coupled to the first input node, and a gate coupled to one of the second output data line pair; and

a second PMOS transistor having a source coupled to the core voltage terminal, a drain coupled to the first input node, and a gate coupled to the other of the second output data line pair.

12. The semiconductor integrated circuit of claim 8 , wherein the output unit comprises a NOR gate configured to output the control signal based on the LSA enable signal and the voltage level on the first input node.

13. The semiconductor integrated circuit of claim 8 , wherein the control signal is configured to limit an activation period of the LSA enable signal to deactivate the LSA, if the detected voltage level reaches a predetermined voltage level.

14. The semiconductor integrated circuit of claim 13 , wherein the predetermined voltage level corresponds to a minimum voltage difference on the second local data line pair that is capable of being sensed by the IOSA.