Semiconductor device having fuse circuit
View Patent ↗A semiconductor device includes a pulse generation circuit configured to generate an enable pulse signal, which is activated in response to an active command signal and deactivated in response to a column command signal, and a plurality of fuse circuits configured to store repair addresses for a column repair and to output stored repair addresses in response to the enable pulse signal.
1. A semiconductor device comprising:
a pulse generation circuit configured to generate an enable pulse signal, which is activated in response to an active command signal and deactivated in response to a column command signal; and
a plurality of fuse circuits configured to store repair addresses for a column repair and to output stored repair addresses in response to the enable pulse signal,
wherein the pulse generation circuit comprises:
a pre-pulse generation unit configured to generate a pre-pulse signal that is activated in response to a pre-charge signal; and
a pre-pulse latch unit configured to latch the pre-pulse signal a column command signal until a column command signal is activated to output the enable pulse signal.
2. The semiconductor device of claim 1 , further comprising;
a column repair decision circuit configured to compare the repair addresses with column addresses received from an external source.
3. The semiconductor device of claim 1 , wherein each of the plurality of fuse circuits comprises:
a fuse unit configured to store a corresponding bit of the repair addresses;
a transfer unit configured to transfer the corresponding bit of the repair addresses stored in the fuse unit in response to the enable pulse signal; and
a latch unit configured to latch an output of the transfer unit.
4. The semiconductor device of claim 1 , wherein each of the plurality of fuse circuits comprises:
a pre-charge unit configured to connect a first node to a first voltage supply terminal in response to a pre-charge signal and to precharge the first node at a first voltage level;
a fuse unit configured to have a fuse and connect a second node to a second voltage supply terminal based on a state of the fuse;
a transfer unit configured to connect the first node to the second node in response to the enable pulse signal; and
a latch unit configured to latch an output corresponding to a voltage level of the first node.
5. The semiconductor device of claim 4 , wherein the first voltage supply terminal includes a power supply voltage terminal and the second voltage supply terminal includes a ground voltage terminal.
6. The semiconductor device of claim 4 , wherein the pulse generation circuit comprises:
a pre-pulse generation unit configured to generate a pre-pulse signal that is activated in response to the pre-charge signal; and
a pre-pulse latch unit configured to latch the pre-pulse signal a column command signal until a column command signal is activated to output the enable pulse signal.
7. A semiconductor device comprising:
a first cell mat configured to be inactive in response to a first cell mat selection signal;
a second cell mat configured to be inactive in response to a second cell mat selection signal;
a pulse generation circuit configured to activate an enable pulse signal in response to an active command and deactivate the enable pulse signal in response to a column command;
at least one fuse circuit configured to store a first repair address for a column repair of the first cell mat and a second repair address for a column repair of the second cell mat, and output the first repair address or the second repair address in response to the enable pulse signal; and
a column repair circuit configured to perform a column repair operation using the first repair address or the second repair address which is output from the at least one fuse circuit.
8. The semiconductor device of claim 7 , wherein the at least one fuse circuit comprises
a first fuse configured to store one bit of the first repair address;
a second fuse configured to one bit of the second repair address;
a transfer unit configured to transfer the first repair address having one bit, which is stored in the first fuse, to an output node in response to the enable pulse signal when the first cell mat selection signal is activated, or the second repair address having one bit, which is stored in the second fuse, to the output node in response to the enable pulse signal when the second cell mat selection signal is activated; and
a latch unit configured to latch the first repair address having one bit or the second repair address having one bit, which is transferred to the output node.
9. The semiconductor device of claim 7 , wherein the at least one fuse circuit comprises
a pre-charge unit configured to connect a first node to a first voltage supply terminal in response to a pre-charge signal and pre-charge the first node to a first voltage level;
a first fuse unit configured to have a first fuse and connect a second node to a first voltage supply terminal according to a cutting state of the first fuse when the first cell mat selection signal is activated;
a second fuse unit configured to have a second fuse and connect the second node to a second voltage supply terminal according to a cutting state of the second fuse when the second cell mat selection signal is activated;
a transfer unit configured to connect the first node to the second node in response to the enable pulse signal; and
a latch unit configured to latch a voltage level of the first node.