Voltage converter and systems including same
View Patent ↗A voltage converter includes an output circuit having a high side device and a low side device which can be formed on a single die (i.e. a “PowerDie”) and connected to each other through a semiconductor substrate. Both the high side device and the low side device can include lateral diffused metal oxide semiconductor (LDMOS) transistors. Because both output transistors include the same type of transistors, the two devices can be formed simultaneously, thereby reducing the number of photomasks over other voltage converter designs. The voltage converter can further include a controller circuit on a different die which can be electrically coupled to, and co-packaged with, the PowerDie.
1. A method for forming a semiconductor device, the method comprising:
providing a single semiconductor substrate;
forming a low side transistor over the single semiconductor substrate, wherein the low side transistor comprises a low side transistor source region, a low side transistor drain region, and a low side transistor gate;
forming a high side transistor over the single semiconductor substrate from the same dopant implants and/or layers as the low side transistor, wherein the high side transistor comprises a high side transistor source region, a high side transistor drain region, and a high side transistor gate;
forming a doped buried layer extending through the low side transistor and the high side transistor;
forming at least one conductive structure;
forming an isolating material that is located within the at least one conductive structure and along at least one sidewall of the at least one conductive structure;
electrically coupling the low side transistor drain region with the semiconductor substrate via one or more of the at least one conductive structures; and
electrically coupling the high side transistor source region with the semiconductor substrate via one or more of the at least one conductive structures.
2. The method of claim 1 , further comprising: electrically coupling the high side transistor drain region to a device voltage in (VIN) pinout; and electrically coupling the low side transistor source region to a device ground (PGND) pinout.
3. The method of claim 1 , further comprising:
implanting both the low side transistor source region and the high side transistor source region using a first implant;
implanting the low side transistor drain region and the high side transistor drain region using a second implant; and
etching the low side transistor gate and the high side transistor gate using the same etch.
4. The method of claim 1 , further comprising:
implanting a low side transistor buried layer and a high side transistor buried layer using the same dopant implantation; and
during the formation of the conductive structure:
etching at least one substrate trench within the single semiconductor substrate;
forming a first substrate trench sidewall and a second substrate trench sidewall during the etching of the at least one substrate trench;
implanting a doped isolation region into the first substrate trench sidewall; and
forming a trench conductor within the substrate trench, wherein, subsequent to forming the trench conductor, the doped isolation region is interposed between the trench conductor and the low side transistor buried layer; and
wherein, subsequent to forming the trench conductor, the second sidewall is interposed between the trench conductor and the high side transistor buried layer and there is no corresponding doped isolation region within the second trench sidewall.
5. The method of claim 1 , further comprising: forming the conductive structure by implanting a sinker region into the single semiconductor substrate.
6. The method of claim 1 , further comprising:
forming the low side transistor and the high side transistor over a front side of the single semiconductor substrate;
forming a conductive layer on a back side of the single semiconductor substrate wherein the low side transistor drain region and the high side transistor source region are electrically connected with the conductive layer on the back side of the single semiconductor substrate; and
wherein an output node of the semiconductor device voltage converter is provided by the conductive layer on the back side of the single semiconductor substrate.