IP Library Granted Patent US 9,444,498
Granted Patent B2
US 9,444,498 · App. 13/718,378 · Granted Sep 13, 2016

Repartitioned transceiver using silicon-on-insulator

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Quick Facts
Patent No.
US 9,444,498
App. No.
13/718,378
Granted
Sep 13, 2016
Kind
B2
Abstract

A transceiver circuit including a digital-to-analog converter, a filter coupled to the digital-to-analog converter, a passive mixer coupled to the filter, via a buffer and a multi-stage power amplifier coupled to the passive mixer via a passive amplifier. A transmitter and method for amplifying a RF signal for transmission are also provided.

Claims (30)

1. A transceiver circuit comprising:

a digital-to-analog converter;

a filter coupled to the digital-to-analog converter;

a passive mixer on a system-on-chip (SOC) die, and coupled to the filter via a buffer; and

a multi-stage power amplifier on a silicon-on-insulator (SOI) die, and coupled to the passive mixer via a passive amplifier, the passive amplifier comprising an inductor, the inductor coupled directly to an output of the passive mixer and directly to an input to the multi-stage power amplifier, the SOC die coupled to the SOI die via the passive amplifier.

2. The transceiver circuit of claim 1 , wherein an output impedance of the passive mixer is less than 50 ohms.

3. The transceiver circuit of claim 1 , wherein the passive amplifier comprises a series network, and wherein the series network comprises one or more inductors and one or more capacitors.

4. The transceiver circuit of claim 1 , wherein the output of the passive amplifier is tapped between the inductor and a capacitor, and

wherein the output of the passive amplifier is coupled to the input of the multi-stage power amplifier.

5. The transceiver circuit of claim 1 , wherein the passive amplifier is configured to operate as a low-pass filter.

6. The transceiver circuit of claim 1 , wherein the mixer is configured to modulate an in-phase signal.

7. The transceiver circuit of claim 1 , wherein the mixer is configured to modulate a quadrature phase signal.

8. The transceiver circuit of claim 1 , wherein an output of the multi-stage power amplifier is coupled to an antenna.

9. A transmitter, comprising:

a digital-to-analog converter;

a filter coupled to the digital-to-analog converter;

a passive mixer on a system-on-chip (SOC) die, and coupled to the filter via a buffer, wherein the buffer comprises an inverter-based feedback amplifier; and

a multi-stage power amplifier on a silicon-on-insulator (SOI) die, and coupled to the passive mixer via a passive amplifier, the passive amplifier comprising an inductor, the inductor coupled directly to an output of the passive mixer and directly to an input to the multi-stage power amplifier, the SOC die coupled to the SOI die via the passive amplifier.

10. The transmitter of claim 9 , wherein an output impedance of the passive mixer is less than 50 ohms.

11. The transmitter of claim 9 , wherein the passive amplifier comprises a series network, and wherein the series network comprises one or more inductors and one or more capacitors.

12. The transmitter of claim 9 , wherein the output of the passive amplifier is tapped between the inductor and a capacitor, and

wherein the output of the passive amplifier is coupled to the input of the multi-stage power amplifier.

13. The transmitter of claim 9 , wherein the passive amplifier is configured to operate as a low-pass filter.

14. A method for amplifying a RF signal for transmission, comprising:

converting a digital signal into an analog signal, using a digital to analog converter;

filtering the analog signal, using a low-pass filter;

mixing, using one or more mixers, the analog signal with a local oscillator signal to produce a modulated RF signal; and

inputting the modulated RF signal to a passive amplifier, wherein an output of the passive amplifier is coupled to a multi-stage power amplifier via an interface, the passive amplifier comprising an inductor, the inductor coupled directly to the one or more mixers and directly to an input to the multi-stage power amplifier,

the one or more mixers implemented on a system-on-chip (SOC) die and the multi-stage power amplifier implemented on a silicon-on-insulator (SOI) die, the SOC die coupled to the SOI die via the passive amplifier.

15. The method of claim 14 , wherein the interface has an impedance of less than 50 ohms.

Assignments (6)
CORRECTIVE ASSIGNMENT TO CORRECT THE EXECUTION DATE PREVIOUSLY RECORDED AT REEL: 047422 FRAME: 0464. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER. Recorded Mar 6, 2019
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 048883/0702 →
MERGER Recorded Oct 5, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047422/0464 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Feb 3, 2017
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: BROADCOM CORPORATION
Reel/Frame 041712/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 1, 2017
From: BROADCOM CORPORATION
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 041706/0001 →
PATENT SECURITY AGREEMENT Recorded Feb 11, 2016
From: BROADCOM CORPORATION
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 037806/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 7, 2013
From: MAGOON, RAHUL; PAN, MICHAEL (MENG-AN); MIRZAEI, AHMAD; MIKHEMAR, MOHYEE
To: BROADCOM CORPORATION
Reel/Frame 029776/0898 →