Semiconductor device with buried bitline and method for fabricating the same

1. A method for fabricating a semiconductor device, the method comprising:

forming active regions on a semiconductor substrate, the active regions being separated by a plurality of first trenches;

forming a support in each first trench of the plurality of first trenches;

defining, by etching the active regions, second trenches that are shallower than the plurality of first trenches;

forming a pair of buried bit lines in each of the second trenches;

forming a first interlayer dielectric layer on bottom and sidewalls of the second trenches; and

forming a second interlayer dielectric layer on the first interlayer dielectric layer, to form an air gap between adjacent the buried bit lines,

wherein the second interlayer dielectric layer is filled over the air gap in a top portion of the second trenches.

2. The method of claim 1 , wherein forming the supports comprises:

forming a dielectric layer on an entire surface to gapfill the first trenches; and

planarizing the dielectric layers.

3. The method of claim 1 , wherein defining the second trenches comprises:

defining second trenches to divide each of the active regions;

forming spacers on sidewalls of the second trenches; and

etching bottoms of the second trenches; and

forming recessed sidewalls in each of the active regions.

4. The method of claim 3 , wherein forming the pair of buried bit lines comprises:

forming a conductive layer on a surface defining the second trenches; and

etching the conductive layer so that the conductive layer remains on the recessed sidewalls in each of the active regions.

5. The method of claim 4 , wherein, after etching the conductive layer, the method further comprises:

recessing bottoms of the second trenches, between pairs of the buried bit lines, to form punch-through preventing patterns.

6. A method for fabricating a semiconductor device, the method comprising:

forming, on a semiconductor substrate, active regions that are separated by a plurality of first trenches;

forming a support in each first trench of the plurality of first trenches;

etching the active regions to define second trenches that are shallower than the plurality of first trenches;

forming spacers on sidewalls of the second trenches;

etching bottoms of the second trenches to define third trenches;

forming punch-through preventing patterns in the third trenches;

etching portions of the sidewalls that are not covered by the punch-through preventing patterns or the spacers, and forming recessed sidewalls which face each other;

forming buried bit lines in the facing recessed sidewalls;

forming a first interlayer dielectric layer on the spacers, the punch-through preventing patterns and the buried bit lines; and

forming a second interlayer dielectric layer on the first interlayer dielectric layer, to form an air gap between adjacent the buried bit lines,

wherein the second interlayer dielectric layer is filled over the air gap in top portion of the second trenches.

7. The method of claim 6 , wherein forming the supports comprises:

forming a dielectric layer on an entire surface to gapfill the first trenches; and

planarizing the dielectric layer.

8. The method of claim 6 , wherein forming the punch-through preventing patterns comprises:

forming a dielectric layer on an entire surface to gapfill the third trenches; and

etching the dielectric layer.

9. The method of claim 6 , wherein forming the buried bit lines comprises:

forming a conductive layer on an entire surface including the recessed sidewalls; and

etching back the conductive layer.