Semiconductor device having a trench structure
View Patent ↗An oxide film is formed by STI in a silicon surface region in which a substrate potential heavily doped diffusion layer and a source heavily doped diffusion layer are to be provided later between trenches at predetermined intervals. The oxide film is removed after the trench is formed, to thereby form a region which is lower than a surrounding surface. Thus, in the vertical MOS transistor having a trench structure which includes a side spacer, a silicide on a gate electrode embedded in the trench and a silicide on the substrate potential heavily doped diffusion layer and the source heavily doped diffusion layer can be separated from each other.
1. A semiconductor device, comprising:
a first conductivity type semiconductor substrate;
a first conductivity type epitaxial growth layer provided on the first conductivity type semiconductor substrate with a second conductivity type buried layer sandwiched therebetween;
a first conductivity type well diffusion layer formed in a part of the first conductivity type epitaxial growth layer on the second conductivity type buried layer;
one of lattice-like trenches and stripe-like trenches which are formed so as to have a depth reaching the second conductivity type buried layer from a surface of the first conductivity type well diffusion layer;
a gate insulating film formed on the trenches;
gate electrodes which fill respective ones of the trenches via the gate insulating film and which protrude higher than the surface of the first conductivity type well diffusion layer;
a side spacer formed on a side surface of the each gate electrode;
a second conductivity type source heavily doped diffusion layer and a first conductivity type substrate potential diffusion layer formed on island-like regions of the first conductivity type well diffusion layer but not on the trenches, wherein the island-like regions have a bottom portion and a surrounding swell region formed thereon, the side spaces are provided on the surrounding swell regions, and the second conductivity type source heavily doped diffusion layer is formed in the surrounding swell regions;
a first silicide layer formed on the gate electrodes; and
a second silicide layer formed on the second conductivity type source heavily doped diffusion layer and the first conductivity type substrate potential diffusion layer, wherein the first silicide layer and the second silicide layer are separated from each other by the side spacers.