Method of manufacturing a semiconductor device
View Patent ↗Forming a photoresist on a region other than a region on a trench gate electrode for a mask, a third gate insulating film on the trench gate electrode is etched and removed. After that, a non-doped polycrystalline silicon layer is formed on second and third gate insulating films and also on the trench gate electrode, and, N-type and P-type high concentration impurities are introduced by an ion implantation with the use of separate masks on the polycrystalline silicon layer of NMOS transistors and PMOS transistors with a low breakdown voltage and a high breakdown voltage. Then, a second gate electrode is formed by anisotropic etching. With the steps as described above, a first gate electrode inside the trench and the second gate electrode to be used in the lateral MOS transistor are laminated, to thereby reduce fluctuations due to the etching.
1. A method of manufacturing a semiconductor device, comprising:
an N-type buried layer forming step of forming an N-type buried layer on a base substrate made of a P-type semiconductor;
an epitaxial growth layer forming step of forming a P-type epitaxial growth layer on the base substrate, to thereby form a semiconductor substrate;
a P-type first well layer forming step of forming a P-type first well layer in a region in which an N-type first lateral MOS transistor having a low breakdown voltage is to be formed;
an N-type first well layer forming step of forming an N-type first well layer in a region in which a P-type second lateral MOS transistor having a low breakdown voltage is to be formed;
a P-type second well layer forming step of forming a P-type second well layer in a region in which an N-type third lateral MOS transistor having a high breakdown voltage is to be formed;
an N-type second well layer forming step of forming an N-type second well layer in each of a region in which a P-type fourth lateral MOS transistor having a high breakdown voltage is to be formed and a region in which an N-type vertical MOS transistor is to be formed;
a body region forming step of forming a P-type body region in a region of the N-type second well layer, in which the N-type vertical MOS transistor is to be formed;
a step of forming, with an insulating film, an element isolation region and an electric field relaxation region of each of the N-type third lateral MOS transistor and the P-type fourth lateral MOS transistor;
a step of forming a first low concentration region in the electric field relaxation region;
a trench forming step of forming a trench in the region in which the N-type vertical MOS transistor is to be formed by performing anisotropic etching toward an inside of the semiconductor substrate so as to have a depth that does not reach the N-type buried layer;
a first gate insulating film forming step of forming a first gate insulating film along a surface of the semiconductor substrate and a wall surface of the trench;
a first polycrystalline silicon layer forming step of forming an N-type first polycrystalline silicon layer on the first gate insulating film;
a first gate electrode forming step of subjecting the N-type first polycrystalline silicon layer to etching to form a first gate electrode inside the trench;
a second gate insulating film forming step of forming a relatively-thick second gate insulating film in a region in which a gate insulating film of each of the N-type third lateral MOS transistor and the P-type fourth lateral MOS transistor is to be formed;
a third gate insulating film forming step of forming a relatively-thin third gate insulating film on the semiconductor substrate for the N-type first lateral MOS transistor and the P-type second lateral MOS transistor;
an etching step of removing the relatively-thin third gate insulating film on the first gate electrode in the trench;
a second polycrystalline silicon layer forming step of forming a non-doped second polycrystalline silicon layer on the semiconductor substrate;
an introducing step of high concentration impurities into the non-doped second polycrystalline silicon layer, of introducing N-type high concentration impurities into the non-doped second polycrystalline silicon layer of each of the N-type first lateral MOS transistor and the N-type third lateral MOS transistor, and introducing P-type high concentration impurities into the non-doped second polycrystalline silicon layer of each of the P-type second lateral MOS transistor and the P-type fourth lateral MOS transistor;
a second gate electrode forming step of subjecting the second polycrystalline silicon layer to etching, to thereby form a second gate electrode on the first gate electrode, and a second gate electrode of each of the N-type first lateral MOS transistor, the P-type second lateral MOS transistor, the N-type third lateral MOS transistor, and the P-type fourth lateral MOS transistor;
a low concentration N-type region forming step of introducing N-type impurities into the region in which the N-type first lateral MOS transistor is to be formed in a self-aligning manner with use of the second gate electrode of the N-type first lateral MOS transistor as a mask, to thereby form a second low concentration N-type impurity region;
a low concentration P-type region forming step of introducing P-type impurities into the region in which the P-type second lateral MOS transistor is to be formed in a self-aligning manner with use of the second gate electrode of the P-type second lateral MOS transistor as a mask, to thereby form a second low concentration P-type impurity region;
an N-type source and drain forming step of introducing N-type impurities into a region of the region in which the N-type first lateral MOS transistor is to be formed, the region being separated from the second gate electrode of the N-type first lateral MOS transistor, and into a region of the region in which the N-type vertical MOS transistor is to be formed, the region being provided in contact with the trench, to thereby form a high concentration N-type impurity region; and
a P-type source and drain forming step of introducing P-type impurities into a region of the region in which the P-type second lateral MOS transistor is to be formed, the region being separated from the second gate electrode of the P-type second lateral MOS transistor, to thereby form a high concentration P-type impurity region.
2. A method of manufacturing a semiconductor device, comprising:
an N-type buried layer forming step of forming an N-type buried layer on a base substrate made of a P-type semiconductor;
an epitaxial growth layer forming step of forming a P-type epitaxial growth layer on the base substrate, to thereby form a semiconductor substrate;
a P-type first well layer forming step of forming a P-type first well layer in a region in which an N-type first lateral MOS transistor having a low breakdown voltage is to be formed;
an N-type first well layer forming step of forming an N-type first well layer in a region in which a P-type second lateral MOS transistor having a low breakdown voltage is to be formed;
a P-type second well layer forming step of forming a P-type second well layer in a region in which an N-type third lateral MOS transistor having a high breakdown voltage is to be formed;
an N-type second well layer forming step of forming an N-type second well layer in a region in which an N-type vertical MOS transistor is to be formed;
a body region forming step of forming a P-type body region in a region of the N-type second well layer, in which the N-type vertical MOS transistor is to be formed;
a step of forming, with an insulating film, an element isolation region and an electric field relaxation region of the N-type third lateral MOS transistor;
a step of forming a first low concentration region in the electric field relaxation region;
a trench forming step of forming a trench in the region in which the N-type vertical MOS transistor is to be formed by performing anisotropic etching toward an inside of the semiconductor substrate so as to have a depth that does not reach the N-type buried layer;
a first gate insulating film forming step of forming a first gate insulating film along a surface of the semiconductor substrate and a wall surface of the trench;
a first polycrystalline silicon layer forming step of forming an N-type first polycrystalline silicon layer on the first gate insulating film;
a first gate electrode forming step of subjecting the N-type first polycrystalline silicon layer to etching to form a first gate electrode inside the trench;
a second gate insulating film forming step of forming a relatively-thick second gate insulating film in a region in which a gate insulating film of the N-type third lateral MOS transistor is to be formed;
a third gate insulating film forming step of forming a relatively-thin third gate insulating film on the semiconductor substrate for the N-type first lateral MOS transistor and the P-type second lateral MOS transistor;
an etching step of removing the relatively-thin third gate insulating film on the first gate electrode in the trench;
a second polycrystalline silicon layer forming step of forming a non-doped second polycrystalline silicon layer on the semiconductor substrate;
an introducing step of high concentration impurities into the non-doped second polycrystalline silicon layer, of introducing N-type high concentration impurities into the non-doped second polycrystalline silicon layer of each of the N-type first lateral MOS transistor and the N-type third lateral MOS transistor, and introducing P-type high concentration impurities into the non-doped second polycrystalline silicon layer of the P-type second lateral MOS transistor;
a second gate electrode forming step of subjecting the second polycrystalline silicon layer to etching, to thereby form a second gate electrode on the first gate electrode, and a second gate electrode of each of the N-type first lateral MOS transistor, the P-type second lateral MOS transistor, and the N-type third lateral MOS transistor;
a low concentration N-type region forming step of introducing N-type impurities into the region in which the N-type first lateral MOS transistor is to be formed in a self-aligning manner with use of the second gate electrode of the N-type first lateral MOS transistor as a mask, to thereby form a second low concentration N-type impurity region;
a low concentration P-type region forming step of introducing P-type impurities into the region in which the P-type second lateral MOS transistor is to be formed in a self-aligning manner with use of the second gate electrode of the P-type second lateral MOS transistor as a mask, to thereby form a second low concentration P-type impurity region;
an N-type source and drain forming step of introducing N-type impurities into a region of the region in which the N-type first lateral MOS transistor is to be formed, the region being separated from the second gate electrode of the N-type first lateral MOS transistor, and into a region of the region in which the N-type vertical MOS transistor is to be formed, the region being provided in contact with the trench, to thereby form a high concentration N-type impurity region; and
a P-type source and drain forming step of introducing P-type impurities into a region of the region in which the P-type second lateral MOS transistor is to be formed, the region being separated from the second gate electrode of the P-type second lateral MOS transistor, to thereby form a high concentration P-type impurity region.
3. A method of manufacturing a semiconductor device, comprising:
an N-type buried layer forming step of forming an N-type buried layer on a base substrate made of a P-type semiconductor;
an epitaxial growth layer forming step of forming a P-type epitaxial growth layer on the base substrate, to thereby form a semiconductor substrate;
a P-type first well layer forming step of forming a P-type first well layer in a region in which an N-type first lateral MOS transistor having a low breakdown voltage is to be formed;
an N-type first well layer forming step of forming an N-type first well layer in a region in which a P-type second lateral MOS transistor having a low breakdown voltage is to be formed;
an N-type second well layer forming step of forming an N-type second well layer in a region in which an N-type vertical MOS transistor is to be formed;
a body region forming step of forming a P-type body region in a region of the N-type second well layer, in which the N-type vertical MOS transistor is to be formed;
a step of forming, with an insulating film, an element isolation region;
a trench forming step of forming a trench in the region in which the N-type vertical MOS transistor is to be formed by performing anisotropic etching toward an inside of the semiconductor substrate so as to have a depth that does not reach the N-type buried layer;
a first gate insulating film forming step of forming a first gate insulating film along a surface of the semiconductor substrate and a wall surface of the trench;
a first polycrystalline silicon layer forming step of forming an N-type first polycrystalline silicon layer on the first gate insulating film;
a first gate electrode forming step of subjecting the N-type first polycrystalline silicon layer to etching to form a first gate electrode inside the trench;
a third gate insulating film forming step of forming a third gate insulating film on the semiconductor substrate for the N-type first lateral MOS transistor and the P-type second lateral MOS transistor;
an etching step of removing the third gate insulating film on the first gate electrode in the trench;
a second polycrystalline silicon layer forming step of forming a non-doped second polycrystalline silicon layer on the semiconductor substrate;
an introducing step of high concentration impurities into the non-doped second polycrystalline silicon layer, of introducing N-type high concentration impurities into the non-doped second polycrystalline silicon layer of the N-type first lateral MOS transistor, and introducing P-type high concentration impurities into the non-doped second polycrystalline silicon layer of the P-type second lateral MOS transistor;
a second gate electrode forming step of subjecting the second polycrystalline silicon layer to etching, to thereby form a second gate electrode on the first gate electrode, and a second gate electrode of each of the N-type first lateral MOS transistor and the P-type second lateral MOS transistor;
a low concentration N-type region forming step of introducing N-type impurities into the region in which the N-type first lateral MOS transistor is to be formed in a self-aligning manner with use of the second gate electrode of the N-type first lateral MOS transistor as a mask, to thereby form a second low concentration N-type impurity region;
a low concentration P-type region forming step of introducing P-type impurities into the region in which the P-type second lateral MOS transistor is to be formed in a self-aligning manner with use of the second gate electrode of the P-type second lateral MOS transistor as a mask, to thereby form a second low concentration P-type impurity region;
an N-type source and drain forming step of introducing N-type impurities into a region of the region in which the N-type first lateral MOS transistor is to be formed, the region being separated from the second gate electrode of the N-type first lateral MOS transistor, and into a region of the region in which the N-type vertical MOS transistor is to be formed, the region being provided in contact with the trench, to thereby form a high concentration N-type impurity region; and
a P-type source and drain forming step of introducing P-type impurities into a region of the region in which the P-type second lateral MOS transistor is to be formed, the region being separated from the second gate electrode of the P-type second lateral MOS transistor, to thereby form a high concentration P-type impurity region.
4. A method of manufacturing a semiconductor device according to claim 1 ,
wherein the introducing of the N-type high concentration impurities in the introducing step of high concentration impurities into the non-doped second polycrystalline silicon layer is carried out simultaneously with the N-type source and drain forming step, and
wherein the introducing of the P-type high concentration impurities in the introducing step of high concentration impurities into the non-doped second polycrystalline silicon layer is carried out simultaneously with the P-type source and drain forming step.
5. A method of manufacturing a semiconductor device according to claim 2 ,
wherein the introducing of the N-type high concentration impurities in the introducing step of high concentration impurities into the non-doped second polycrystalline silicon layer is carried out simultaneously with the N-type source and drain forming step, and
wherein the introducing of the P-type high concentration impurities in the introducing step of high concentration impurities into the non-doped second polycrystalline silicon layer is carried out simultaneously with the P-type source and drain forming step.
6. A method of manufacturing a semiconductor device according to claim 3 ,
wherein the introducing of the N-type high concentration impurities in the introducing step of high concentration impurities into the non-doped second polycrystalline silicon layer is carried out simultaneously with the N-type source and drain forming step, and
wherein the introducing of the P-type high concentration impurities in the introducing step of high concentration impurities into the non-doped second polycrystalline silicon layer is carried out simultaneously with the P-type source and drain forming step.