Active area shaping for III-nitride devices
A III-nitride heterojunction power semiconductor device that includes a passivation body with a gate well having a top mouth that is wider than the bottom mouth thereof, and a method of fabrication for the same.
1. A III-nitride semiconductor device comprising:
a first III-nitride body having one band gap, and a second III-nitride body having another band gap disposed over said first III-nitride body;
a first insulation body situated over said second III-nitride body, and a second insulation body situated over said first insulation body;
a gate well having a first mouth defined in said first insulation body by ledges that extend laterally toward an interior of said gate well, and a second mouth defined in said second insulation body, said second mouth being wider than said first mouth;
a gate arrangement disposed at least partially within said gate well, said gate arrangement including a gate dielectric formed along said first mouth and said second mouth in said gate well, and a gate electrode over said gate dielectric, said gate arrangement filling said gate well.
2. The III-nitride semiconductor device of claim 1 , further comprising a drain electrode and a source electrode on respective sides of said gate arrangement.
3. The III-nitride semiconductor device of claim 1 , wherein said first insulation body comprises silicon nitride.
4. The III-nitride semiconductor device of claim 1 , wherein said second insulation body comprises a nitride dielectric.
5. The III-nitride semiconductor device of claim 1 , wherein said second insulation body comprises silicon nitride.
6. The III-nitride semiconductor device of claim 1 , wherein said second insulation body comprises aluminum nitride.
7. The III-nitride semiconductor device of claim 1 , wherein said second insulation body comprises titanium nitride.
8. The III-nitride semiconductor device of claim 1 , wherein said first III-nitride body comprises GaN and said second III-nitride body comprises AlGaN.
9. A method of fabricating a III-nitride semiconductor device, said method comprising:
forming a first III-nitride body having one band gap, and a second III-nitride body having another band gap disposed over said first III-nitride body;
forming a first insulation body over said second III-nitride body;
forming a second insulation body situated over said first insulation body;
forming a gate well having a first mouth defined in said first insulation body by ledges that extend laterally toward an interior of said gate well, and a second mouth defined in said second insulation body, said second mouth being wider than said first mouth;
forming a gate dielectric along said first mouth and said second mouth in said gate well;
forming a gate electrode over said gate dielectric.
10. The method of claim 9 , further comprising forming a drain electrode and a source electrode on respective sides of said gate electrode.
11. The method of claim 9 , wherein said first insulation body comprises silicon nitride.
12. The method of claim 9 , wherein said second insulation body comprises a nitride dielectric.
13. The method of claim 9 , wherein said second insulation body comprises silicon nitride.
14. The method of claim 9 , wherein said second insulation body comprises aluminum nitride.
15. The method of claim 9 , wherein said second insulation body comprises titanium nitride.
16. The method of claim 9 , wherein said first III-nitride body comprises GaN and said second III-nitride body comprises AlGaN.