Management of non-valid decision patterns of a soft read retry operation
View Patent ↗An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to generate an output signal in response to (i) a value retrieved from a look-up table, and (ii) an index signal. The second circuit may be configured to generate the index signal in response to a plurality of page signals. The apparatus may manage decision patterns during a soft retry.
1. An apparatus comprising:
a first circuit configured to generate an output value by addressing a look-up table with an index signal, wherein said output value is useable in a soft decode of data; and
a second circuit configured to generate said index signal in response to (i) a plurality of bits received from a plurality of hard reads of said data from a memory cell over a plurality of voltages, wherein a sequence of said bits forms a decision pattern, (ii) a determination of a validity of said decision pattern based on a number of said hard reads and (iii) a correction of said decision pattern if said decision pattern is determined to be invalid, wherein said index signal identifies one of a plurality of valid patterns that matches said decision pattern.
2. The apparatus according to claim 1 , wherein said index signal comprises a multi-bit index signal.
3. The apparatus according to claim 1 , wherein (i) said look-up table stores a plurality of soft values received from a third circuit, and (ii) said output value is one of said soft values identified by said index signal.
4. The apparatus according to claim 1 , wherein said apparatus is implemented as part of a memory controller.
5. The apparatus according to claim 4 , wherein said memory controller comprises a solid state drive memory controller.
6. The apparatus according to claim 1 , wherein said correction adjusts said decision pattern to an erasure state of one of said valid patterns.
7. The apparatus according to claim 1 , wherein said correction is based on a probability that said decision pattern is one of said valid patterns with one or more errors in said sequence of said bits.
8. The apparatus according to claim 7 , wherein said probability is determined by a number of said bits in said decision pattern that are flipped relative to said one valid pattern.
9. The apparatus according to claim 1 , wherein said correction adjusts said decision pattern to one of said valid patterns with a lowest number of said bits that are flipped relative to said valid patterns.
10. The apparatus according to claim 9 , wherein said one valid pattern has a minimum Hamming distance from said decision pattern.
11. The apparatus according to claim 1 , wherein said correction adjusts said decision pattern to one of said valid patterns between two of said valid patterns both with a lowest number of said bits that are flipped relative to said valid patterns.
12. A method for management of non-valid decision patterns, comprising the steps of:
(A) receiving a plurality of bits from a plurality of hard reads of data from a memory cell over a plurality of voltages, wherein a sequence of said bits forms a decision pattern;
(B) generating an index signal in response to (i) a determination of a validity of said decision pattern based on a number of said hard reads and (ii) a correction of said decision pattern if said decision pattern is determined to be invalid, wherein said index signal identifies one of a plurality of valid patterns that matches said decision pattern; and
(C) generating an output value by addressing a look-up table with said index signal, wherein said output value is useable in a soft decode of data.
13. The method according to claim 12 , wherein said correction adjusts said decision pattern to an erasure state of one of said valid patterns.
14. The method according to claim 12 , wherein said correction is based on a probability that said decision pattern is one of said valid patterns with one or more errors in said sequence of said bits.
15. The method according to claim 14 , wherein said probability is determined by a number of said bits in said decision pattern that are flipped relative to said one valid pattern.
16. The method according to claim 12 , wherein said correction adjusts said decision pattern to one of said valid patterns with a lowest number of said bits that are flipped relative to said valid patterns.
17. The method according to claim 12 , wherein said correction adjusts said decision pattern to one of said valid patterns between two of said valid patterns both with a lowest number of said bits that are flipped relative to said valid patterns.
18. The method according to claim 12 , wherein said validity of said decision pattern is further based on a current one of a plurality of pages in said memory cell where said data is stored.
19. An apparatus comprising:
a memory configured to process a plurality of read/write operations; and
a controller configured to (i) receive a plurality of bits from a plurality of hard reads of data from a memory cell of said memory over a plurality of voltages, wherein a sequence of said bits forms a decision pattern, (ii) generate an index signal in response to (a) a determination of a validity of said decision pattern based on a number of said hard reads and (b) a correction of said decision pattern if said decision pattern is determined to be invalid, wherein said index signal identifies one of a plurality of valid patterns that matches said decision pattern, and (iii) generate an output value by addressing a look-up table with said index signal, wherein said output value is useable in a soft decode of said data.
20. The apparatus according to claim 19 , wherein said apparatus comprises a solid state drive.