Semiconductor device having multi-level wiring structure
View Patent ↗Disclosed herein is a device that includes a multi-level wiring structure including a first wiring layer and a second wiring layer formed over the first wiring layer; a memory cell array area including a plurality of memory cells, a plurality of sense amplifiers and a plurality of sub amplifiers; a main amplifier area including a plurality of main amplifiers, the memory cell array area and the main amplifier area being arranged in line in a first direction; and a plurality of first I/O lines each connecting an associated one of the sub amplifiers to an associated one of the main amplifiers, each of the first I/O lines including first and second wiring portions that are elongated in the first direction, the first wiring portion being formed as the first wiring layer and the second wiring portion being formed as the second wiring layer.
1. A semiconductor device comprising:
a memory mat having a plurality of bit lines each extending in a first direction, a plurality of word each lines extending in a second direction crossing to the first direction, and a plurality of memory cells arranged respectively at intersections of the bit lines and the word lines;
a plurality of sense amplifiers coupled respectively to the bit lines, the sense amplifiers being provided in a sense amplifier area that is adjacent to the memory mat in the first direction;
a plurality of column selection lines extending in the first direction as a first wiring layer;
a local I/O line extending in the second direction as a second wiring layer;
a plurality of main I/O lines extending in the first direction, the main I/O lines being provided as a third wiring layer over the sense amplifier area and provided as the first wiring layer over the memory mat; and
a power-supply line extending in the first direction as the third wiring layer, a part of the power-supply line overlapping with the main I/O lines provided over the memory mat.
2. The semiconductor device as claimed in claim 1 , wherein an arrangement pitch of the column selection lines over the memory mat is narrower than an arrangement pitch thereof over the sense amplifier area to secure an empty space on the first wiring layer, the main I/O lines are arranged in the empty space in the first wiring layer over the memory mat.
3. The semiconductor device as claimed in claim 2 , wherein the column selection lines have a roundabout pattern to form the empty space on a central part of the memory mat in the second direction.
4. The semiconductor device as claimed in claim 2 , herein the column selection lines have a roundabout pattern to form the empty space on an end side of the memory mat in the second direction.
5. The semiconductor device as claimed in claim 1 , further comprising a plurality of contact plugs each connected between an associated one of the main I/O lines provided as the first wiring layer and the associated one of the main I/O lines provided as the third wiring layer.
6. The semiconductor device as claimed in claim 1 , wherein two column selection lines are arranged between adjacent two main I/O lines formed as the first wiring layer over the memory mat.
7. The semiconductor device as claimed in claim 1 , wherein
the power-supply line includes a first section that overlapping with the main I/O lines and a plurality of second sections elongated from the first section to the first direction, each of the second section is narrower in width than the first section,
the main I/O lines and the second sections of the power-supply line are alternately arranged in the second direction on the first wiring layer, and
the first and second sections of the power-supply line are short-circuited to constitute a single line that extends in the first direction.
8. The semiconductor device as claimed in claim 1 , wherein the power-supply line is supplied with an external power-supply potential.