IP Library Granted Patent US 8,762,917
Granted Patent B2
US 8,762,917 · App. 13/723,773 · Granted Jun 24, 2014

Automatically modifying a circuit layout to perform electromagnetic simulation

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 8,762,917
App. No.
13/723,773
Granted
Jun 24, 2014
Kind
B2
Abstract

Automatically modifying a layout to perform circuit simulation. Initially, a first layout of the electronic system may be received or stored. A second layout of the electronic system may be automatically generated based on the first layout. The automatic generation may involve automatically simplifying the first layout using a set of rules for electromagnetic (EM) simulation. The second layout may then be used to perform EM simulation of the electronic system, e.g., to perform verification.

Claims (36)

1. A method for automatically modifying an electronic system, comprising:

storing a first layout of the electronic system in a memory;

automatically generating a second layout of the electronic system based on the first layout, wherein said automatically generating the second layout comprises automatically modifying the first layout in accordance with a set of rules that specify requirements for electromagnetic (EM) simulation; and

storing the second layout of the electronic system in the memory, wherein the second layout is usable to perform the EM simulation of the electronic system, wherein EM simulation of the electronic system per the second layout is simpler than EM simulation of the electronic system per the first layout.

2. The method of claim 1 , further comprising:

performing EM simulation of the electronic system using the second layout.

3. The method of claim 2 , further comprising:

verifying the electronic system based on said performing the EM simulation.

4. The method of claim 1 , wherein said automatically generating the second layout of the electronic system comprises automatically removing features of the first layout.

5. The method of claim 1 , wherein said automatically generating the second layout of the electronic system comprises automatically moving one or more ports from first locations in the first layout to second, different, locations in the second layout.

6. The method of claim 1 , further comprising:

receiving user input to modify the set of rules; and

modifying the set of rules in response to the user input.

7. The method of claim 1 , wherein the set of rules are selecting from a plurality of sets of rules, wherein the method further comprises:

selecting the set of rules from the plurality of sets of rules.

8. The method of claim 7 , wherein the first layout is associated with a first foundry, wherein the set of rules is associated with the first foundry, wherein said selecting the set of rules is based on the first layout and the set of rules being associated with the first foundry.

9. The method of claim 7 , wherein the first layout is associated with a first circuit creation process, wherein the set of rules is associated with the first circuit creation process, wherein said selecting the set of rules is based on the first layout and the set of rules being associated with the first circuit creation process.

10. The method of claim 1 , wherein the electronic system comprises a circuit or a circuit board.

11. A non-transitory computer accessible memory medium storing program instructions for a automatically modifying a layout of an electronic system, wherein the program instructions are executable to:

receive a first layout of the electronic system;

automatically generate a second layout of the electronic system based on the first layout, wherein said automatically generating the second layout comprises automatically modifying the first layout in accordance with a set of rules that specify requirements for electromagnetic (EM) simulation; and

store the second layout of the electronic system, wherein the second layout is usable to perform EM simulation of the electronic system, wherein EM simulation of the electronic system per the second layout is simpler than EM simulation of the electronic system per the first layout.

12. The non-transitory computer accessible memory medium of claim 11 , wherein the program instructions are further executable to:

perform EM simulation of the electronic system using the second layout.

13. The non-transitory computer accessible memory medium of claim 12 , wherein the program instructions are further executable to:

verify the electronic system based on said performing the EM simulation.

14. The non-transitory computer accessible memory medium of claim 11 , wherein said automatically generating the second layout of the electronic system comprises automatically removing features of the first layout.

15. The non-transitory computer accessible memory medium of claim 11 , wherein said automatically generating the second layout of the electronic system comprises automatically moving one or more ports from first locations in the first layout to second, different, locations in the second layout.

16. The non-transitory computer accessible memory medium of claim 11 , wherein the program instructions are further executable to:

receive user input to modify the set of rules; and

modify the set of rules in response to the user input.

17. The non-transitory computer accessible memory medium of claim 11 , wherein the set of rules are selecting from a plurality of sets of rules, wherein the program instructions are further executable to:

select the set of rules from the plurality of sets of rules.

18. The non-transitory computer accessible memory medium of claim 17 , wherein the first layout is associated with a first foundry, wherein the set of rules is associated with the first foundry, wherein said selecting the set of rules is based on the first layout and the set of rules being associated with the first foundry.

19. The non-transitory computer accessible memory medium of claim 17 , wherein the first layout is associated with a first circuit creation process, wherein the set of rules is associated with the first circuit creation process, wherein said selecting the set of rules is based on the first layout and the set of rules being associated with the first circuit creation process.

20. The non-transitory, computer accessible memory medium of claim 11 , wherein the electronic system comprises a circuit or a circuit board.

Assignments (6)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 8, 2024
From: AWR LLC
To: CADENCE DESIGN SYSTEMS, INC.
Reel/Frame 066414/0891 →
RELEASE OF SECURITY INTEREST IN PATENTS (REEL/FRAME 057280/0028) Recorded Oct 13, 2023
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS ADMINISTRATIVE AGENT
To: NATIONAL INSTRUMENTS CORPORATION
Reel/Frame 065231/0466 →
RELEASE OF SECURITY INTEREST IN PATENTS (REEL/FRAME 052935/0001) Recorded Oct 13, 2023
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS ADMINISTRATIVE AGENT
To: NATIONAL INSTRUMENTS CORPORATION; PHASE MATRIX, INC.
Reel/Frame 065653/0463 →
SECURITY INTEREST Recorded Jun 18, 2021
From: NATIONAL INSTRUMENTS CORPORATION
To: WELLS FARGO BANK, NATIONAL ASSOCIATION
Reel/Frame 057280/0028 →
SECURITY INTEREST Recorded Jun 14, 2020
From: NATIONAL INSTRUMENTS CORPORATION; PHASE MATRIX, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION
Reel/Frame 052935/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 21, 2012
From: PEKAREK, JOSEPH EDWARD; DODDAMANI, NIRANJANA SHARMA
To: AWR CORPORATION
Reel/Frame 029517/0614 →