IP Library Granted Patent US 9,065,755
Granted Patent B2
US 9,065,755 · App. 13/724,361 · Granted Jun 23, 2015

Low-latency switching

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Quick Facts
Patent No.
US 9,065,755
App. No.
13/724,361
Granted
Jun 23, 2015
Kind
B2
Abstract

Disclosed are systems and methods for cut-through switching in port-speed-mismatched networks. Specifically, systems and methods are described in which data packets from an ingress device are paced, thereby matching the data rate of the ingress device with the data rate of the egress device.

Claims (47)

1. A system, comprising:

an egress device having an egress transmission rate, the egress device comprising:

a cut-through buffer for cut-through switching of the data packets; and

a store-and-forward buffer for store-and-forward switching of the data packets;

an ingress device having an ingress transmission rate, the ingress device comprising a virtual output queue, the virtual output queue having a buffer size, the ingress device configured to:

determine whether the ingress transmission rate is faster than the egress transmission rate;

determine whether the buffer size exceeds a first threshold value; and

in response to determining that the ingress transmission rate is faster than the egress transmission rate, and further in response to determining that the buffer size exceeds the first threshold value:

capture cut-through eligibility to an egress port for cut-through switching; and

pace the data packets to match the egress transmission rate.

2. The system of claim 1 , the ingress device further configured to:

determine whether the buffer size exceeds a second threshold value, the second threshold value being greater than the first threshold value; and

in response to determining that the buffer size exceeds the second threshold value, transition to a store-and-forward mode for store-and-forward switching from a cut-through mode.

3. The system of claim 1 , further comprising:

a packet shaper located on an output of the ingress device, the packet shaper configured to pace the data packets.

4. A system comprising:

an egress device for cut-through transmission of packets, the egress device configured to transmit the packets at an egress transmission rate;

an ingress device including a virtual output queue having a buffer size, the ingress device configured to:

determine whether an ingress transmission rate of the ingress device is faster than the egress transmission rate;

determine whether the buffer size exceeds a first threshold value; and

capture cut-through eligibility for cut-through switching and control a packet shaper to pace the packets from the ingress device to match the egress transmission rate when the ingress transmission rate is faster than the egress transmission rate and the buffer size exceeds the first threshold.

5. The system of claim 4 , wherein the packet shaper is interposed between the ingress device and the egress device.

6. The system of claim 4 , wherein the packet shaper is operatively coupled to the ingress device.

7. The system of claim 6 , wherein the packet shaper is directly connected to an output of the ingress device.

8. The system of claim 4 , wherein the packet shaper is operatively coupled to the egress device.

9. The system of claim 4 , the egress device comprising:

a cut-through buffer for cut-through switching of the packets; and

a store-and-forward buffer for store-and-forward switching of the packets.

10. The system of claim 4 , wherein the packet shaper is responsive to the ingress device, the packet shaper being configured to pace the packets when the buffer size exceeds the first threshold value.

11. The system of claim 4 , wherein the ingress device is further configured to determine whether the buffer size exceeds a second threshold value, the second threshold value being larger than the first threshold value.

12. The system of claim 11 , wherein the ingress device is further configured to transition to a store-and-forward mode for store-and-forward switching from a cut-through mode when the buffer size exceeds the second threshold value.

13. An ingress device comprising:

a virtual output queue having a buffer size; and

circuitry configured to

determine whether an ingress transmission rate of the ingress device is faster than an egress transmission rate of an egress device;

determine whether the buffer size exceeds a first threshold value;

and capture cut-through-eligibility of the egress device;

and pace a packet to match the ingress transmission rate of the ingress device with the egress transmission rate when the ingress transmission rate is faster than the egress transmission rate and the buffer size exceeds the first threshold value.

14. The ingress device of claim 13 , wherein the circuitry is configured to:

determine whether the buffer size exceeds a second threshold value; and

transition to store-and-forward switching when the buffer size exceeds the second threshold value.

15. The ingress device of claim 13 , wherein the circuitry is configured to bypass cut-through switching in response to determining that the ingress transmission rate is slower than the egress transmission rate.

16. The ingress device of claim 13 , further comprising:

a memory, wherein

the circuitry is configured by executing software or firmware stored in the memory.

17. The ingress device of claim 13 , wherein

the circuitry is at least one of: one or more discrete logic circuits, one or more application specific integrated circuit (ASIC), one or more programmable gate arrays (PGA) and one or more field programmable gate arrays (FPGA).

Assignments (7)
CORRECTIVE ASSIGNMENT TO CORRECT THE PATENT NUMBER 9,385,856 TO 9,385,756 PREVIOUSLY RECORDED AT REEL: 47349 FRAME: 001. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER. Recorded Mar 22, 2019
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 051144/0648 →
CORRECTIVE ASSIGNMENT TO CORRECT THE EFFECTIVE DATE PREVIOUSLY RECORDED ON REEL 047229 FRAME 0408. ASSIGNOR(S) HEREBY CONFIRMS THE THE EFFECTIVE DATE IS 09/05/2018. Recorded Oct 29, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047349/0001 →
MERGER Recorded Oct 4, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047229/0408 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Feb 3, 2017
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: BROADCOM CORPORATION
Reel/Frame 041712/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 1, 2017
From: BROADCOM CORPORATION
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 041706/0001 →
PATENT SECURITY AGREEMENT Recorded Feb 11, 2016
From: BROADCOM CORPORATION
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 037806/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 6, 2013
From: KWAN, BRUCE; AGARWAL, PUNEET
To: BROADCOM CORPORATION
Reel/Frame 029762/0725 →