Memory device with internal combination logic

1. A memory integrated circuit (IC), comprising:

a data access component configured to provide an address;

a memory array, coupled to the data access component, configured to receive the address provided by the data access component and provide data stored at a location associated with the address;

a data holding component, coupled to the memory array, configured to receive the data provided by the memory array; and

a logic component, coupled to the data access component and the data holding component, unrelated to the memory array, configured to receive the data from the data holding component, execute a dedicated task using the data, and determine if an exit condition has been met, wherein the exit condition tests whether a search string has been found or whether an end of a graph has been encountered.

2. The memory IC of claim 1 , wherein:

the logic component is connected to the data access component; and

the logic component is further configured to indicate that the exit condition has not been met to the data access component when the logic component determines that the exit condition has not been met.

3. The memory IC of claim 2 , wherein data access component is further configured to modify the address provided to the memory array when it receives an indication that the exit condition has not been met.

4. The memory IC of claim 1 , further comprising a results component, connected to the logic component, configured to store a final result from the logic component when the exit condition has been met.

5. The memory IC of claim 1 , wherein the logic component further comprises:

a first combinational logic block and a second combinational logic block; and

a staging register;

wherein the staging register receives an input from the first combinational logic block and sends an output to the second combinational logic block.

6. The memory IC of claim 1 , further comprising:

input registers and output registers connected to the data access component and the logic component respectively; and

at least two clocks, wherein a first clock is connected to the input and output registers and a second clock is connected to the memory array, data access component, data holding component, and logic component.

7. The memory IC of claim 1 , wherein the memory array consists of non-volatile memory.

8. The memory IC of claim 1 , wherein the task executed by the logic component does not modify any data in the memory array.

9. The memory IC of claim 1 , wherein the task executed by the logic component processes multiple bytes of data in parallel by taking advantage of a wide bus of the memory IC.

10. A method for processing data within a memory integrated circuit (IC), the memory IC comprising a memory array and a logic component unrelated to the function of the memory array, comprising:

determining a memory address;

retrieving data from the memory array at the memory address;

executing a dedicated task using the data to produce a result; and

returning the result if the result satisfies an exit condition, wherein the exit condition tests whether a search string has been found or whether an end of a graph has been encountered.

11. The method of claim 10 , further comprising receiving initial external data from an external source, wherein the determining uses the initial external data.

12. The method of claim 10 , further comprising receiving a second data from an external source wherein the executing uses the second data.

13. The method of claim 10 , wherein the executing takes more than one clock cycle and the executing is pipelined to allow multiple data to be handled substantially concurrently.

14. The method of claim 10 , wherein the executing does not modify the memory array.

15. The method of claim 10 , wherein the executing processes multiple bytes of data in parallel.

16. A system, comprising:

a central processing unit (CPU); and

a system memory integrated circuit (IC) coupled to the CPU, wherein the system memory IC comprises:

an data access component configured to provide an address a memory array, coupled to the data access component, configured to receive the address provided by the data access component and provide data stored at a location associated with the address;

a data holding component configured to receive the data from the memory array; and

a logic component, unrelated to the memory array, configured to receive the data from the data holding component, execute a task using the data, and determine if an exit condition has been met, wherein the exit condition tests whether a search string has been found or whether an end of a graph has been encountered.

17. The system of claim 16 , wherein:

the logic component is connected to the data access component; and

the logic component is further configured to indicate that the exit condition has not been met to the data access component when the logic component determines that the exit condition has not been met.

18. The system of claim 16 , wherein the logic component further comprises:

a first combinational logic block and a second combinational logic block; and

a staging register;

wherein the staging register receives an input from the first combinational logic block and sends an output to the second combinational logic block.

19. The system of claim 16 , wherein the memory array consists of non-volatile memory.

20. The system of claim 16 , wherein the task executed by the logic component does not modify any data in the memory array.