A substantially rectangular display panel includes a first edge extending in a first major axis direction of the rectangular shape and a second edge extending in a second major axis direction of the rectangular shape, the second direction being different from the first direction. The display panel includes: a plurality of gate lines extending in the first direction; and a gate lines driver including a plurality of main stages sequentially connected to each other and configured for outputting gate signals to the gate lines, where the plurality of stages further includes one or more dummy stages arranged in a row along the second edge and not connected to the plurality of gate lines, and where a layout arrangement of a plurality of thin film transistors included in the main stage is different from a corresponding layout arrangement of corresponding thin film transistors included in the at least one dummy stage.
1. A substantially rectangular display panel having a first edge extending in a first direction and a second edge extending in a second direction, the first and second directions being major axes of the substantially rectangular shape of the display panel, where the display panel is subdivided into a display area and a peripheral area and comprises:
a plurality of gate lines extending in the second direction in the display area; and
a gate lines driver including a plurality of main stages sequentially arranged in the first direction in the peripheral area and configured for outputting respective gate signals to respective ones of the gate lines,
wherein the gate lines driver further includes one or more dummy stages not connected to the gate lines of the display area;
wherein the main stages arranged alongside the first edge;
wherein at least one of the main stages connects to at least one dummy stage disposed in a row area alongside the second edge, and
wherein the at least one dummy stage is longer in the second direction than in the first direction.
2. The display panel of claim 1 , wherein one of the main stages includes a first plurality of transistors, and one of the at least one dummy stage includes a second plurality of transistors, and
wherein a relative arrangement of the first plurality of transistors is different from a relative arrangement of the second plurality of transistors.
3. The display panel of claim 2 , further comprising
a control signal line transmitting a control signal to the plurality of main stages and the at least one dummy stages,
wherein the control signal line includes a first portion extending along the first edge, a second portion extending along the second edge, and a corner portion connecting the first portion and the second portion, and
the corner portion forms an oblique angle with the first direction and the second direction.
4. The display panel of claim 3 , wherein
the control signal line includes at least one of a clock signal line, a scanning start signal line, and a low voltage line.
5. The display panel of claim 4 , further comprising
an alignment key is positioned between the corner portion of the control signal line and at least one of the first edge and the second edge.
6. The display panel of Claim 1 , further comprising
a dummy loads pattern connected to the at least one dummy stage and neighboring the at least one dummy stage in the row area alongside the second edge.
7. The display panel of claim 6 , wherein
the at least one dummy stage includes an output terminal outputting a dummy gate signal, and
the dummy loads pattern includes one or more electric load elements connected to the output terminal of the dummy stage.
8. The display panel of claim 1 , wherein
a length in the second direction of the at least one dummy stage is longer than a length in the first direction and a length in the second direction of the at least one main stage.
9. The display panel of claim 8 , wherein
a first thin film transistor of one of the main stages includes a plurality of first unit subtransistors connected in parallel,
a respective second thin film transistor provided in one of the dummy stages and respectively performing a substantially same function as the first thin film transistor includes a plurality of second unit subtransistors that are connected in parallel,
a channel width of one of the plurality of first unit subtransistors is different from a channel width of one of the plurality of second unit subtransistors.
10. The display panel of claim 9 , wherein
a channel width of one of the plurality of first unit transistors is less than a channel width of one of the plurality of second unit transistors.
11. The display panel of claim 1 , wherein
the at least one dummy stage is connected to at least one main stage among the plurality of main stages through corner wiring, and
the corner wiring forms an oblique angle with the first direction and the second direction.
12. The display panel of claim 1 , wherein
the display area is configured for displaying an image and the peripheral area is disposed around the display area, and
at least a portion of the plurality of thin film transistors of the at least one main stage is positioned in the display area.
13. The display panel of claim 1 , wherein
the display panel further includes a third edge facing the first edge, and
the plurality of stages of the gate lines driver further include a plurality of main stages arranged in a column along the third edge and connected to the plurality of gate lines, and at least one dummy stage connected to the plurality of main stages arranged along the third edge.
14. The display panel of claim 13 , further comprising
a dummy loads pattern connected to an output terminal of the at least one dummy stage connected to the plurality of main stages arranged along the third edge.
15. The display panel of claim 1 , wherein
the display area is configured for displaying an image and the peripheral area is disposed around the display area, and
the gate lines driver includes a third portion positioned in the peripheral area and a fourth portion positioned in the display area.
16. The display panel of claim 15 , wherein
the fourth portion includes at least one active element.
17. The display panel of claim 1 , wherein
a length in the first direction of one dummy stage among the at least one dummy stage is less than a length in the first direction of one main stage among the plurality of main stages.
18. The display panel of claim 17 , wherein
an area of a dummy stage is different from an area of a main stage.
19. The display panel of claim 17 , wherein
the dummy stages includes at least two dummy stages having different areas.
20. The display panel of claim 17 , wherein
a length in the first direction of one dummy stage among the at least one dummy stage is less than a length in the second direction of the one dummy stage.
21. A display panel having a first edge extending in a first direction and a second edge extending in a second direction, where the display panel is subdivided into a display area and a peripheral area and comprises:
a plurality of gate lines extending in the second direction in the display area; and
a gate lines driver including a plurality of main stages sequentially arranged in the first direction in the peripheral area and configured for outputting respective gate signals to respective ones of the gate lines,
wherein the gate lines driver further includes one or more dummy stages not connected to the gate lines of the display area;
wherein the main stages arranged alongside the first edge;
wherein at least one of the main stages connects to at least one dummy stage disposed in a row area alongside the second edge,
wherein the at least one dummy stage is longer in the second direction than in the first direction, and
wherein
a first thin film transistor of a plurality of thin film transistors of the at least one main stage includes a first plurality of first unit subtransistors connected in parallel,
a respective second thin film transistor provided in the at least one dummy stage and respectively performing a substantially same function as the first thin film transistor includes a second plurality of second unit subtransistors that are connected in parallel, and
the first plurality has a different number of unit subtransistors than does the second plurality.
22. The display panel of claim 21 , wherein
an elongation direction of an elongated channel of one of the plurality of first unit subtransistors is different from an elongation direction of an elongated channel of one of the plurality of second unit subtransistors.
23. The display panel of claim 22 , wherein
the elongation direction of the elongated channel of one of the plurality of second unit subtransistors is the second direction.
24. The display panel of claim 23 , wherein
a length in the second direction of the dummy stage is longer than a length in the first direction of the at least one main stage and the length in the second direction of the dummy stage is also longer than a length in the second direction of the at least one main stage.
25. The display panel of claim 24 , wherein
a channel width of one of the plurality of first unit subtransistors is different from a channel width of one of the plurality of second unit subtransistors.
26. The display panel of claim 25 , wherein
a channel width of one of the plurality of first unit subtransistors is less than a channel width of one of the plurality of second unit subtransistors.
27. The display panel of claim 26 , further comprising
a control signal line configured for transmitting a control signal to the plurality of main stages and to the at least one dummy stage,
wherein the control signal line includes a first portion extending along the first edge, a second portion extending along the second edge, and a corner portion connecting the first portion to the second portion, and
wherein the corner portion forms an oblique angle with the first direction and with the second direction.
28. The display panel of claim 27 , wherein
the control signal line includes at least one of a clock signal line, a scanning start signal line, and a low voltage line.
29. The display panel of claim 28 , wherein
the at least one dummy stage is connected to at least one main stage among the plurality of main stages through the corner portion of the control signal line.
30. The display panel of claim 29 , further comprising
an alignment key positioned between the corner portion of the control signal line and at least one of the first edge and the second edge.
31. The display panel of claim 30 , wherein
the display area is configured for displaying an image and the peripheral area is disposed around the display area, and
at least a portion of the plurality of thin film transistors of the at least one main stage is positioned in the display area.
32. The display panel of claim 31 , wherein
a first thin film transistor of the plurality of thin film transistors of the at least one main stage includes a first plurality of first unit subtransistors,
a second thin film transistor performing a substantially same function as the first thin film transistor among the plurality of thin film transistors of the at least one dummy stage includes a second plurality of second unit subtransistors, and
the first plurality has a number of corresponding first unit subtransistors that is different from a number of corresponding second unit subtransistors forming the second plurality.
33. The display panel of claim 32 , wherein
a first thin film transistor of the plurality of thin film transistors of the at least one main stage includes a first plurality of corresponding first unit subtransistors,
a second thin film transistor performing a substantially same function as the first thin film transistor among the plurality of thin film transistors of the at least one dummy stage includes a second plurality of corresponding second unit subtransistors, and
an elongation direction of an elongated channel of one of the plurality of first unit subtransistors is different from an elongation direction of an elongated channel of one of the plurality of second unit subtransistors.
34. The display panel of claim 33 , wherein
the elongation direction of the elongated channel of one of the plurality of second unit subtransistors is the second direction.