Accumulating LDPC (low density parity check) decoder
View Patent ↗The accumulating decoding architecture described herein is applicable to LDPC codes operating on a parity check matrix, H, consisting of CSI (Cyclic Shifted Identity) sub-matrices (or matrix sub-blocks) or permuted identity sub-matrices (or matrix sub-blocks). In such a structure, the entire LDPC matrix is broken into square sub-matrices such that each sub-matrix consists of either a CSI sub-matrix or a permuted identity sub-matrix, or a null matrix. The iterative decoding process operates by updating of APP (a posteriori probability) or gamma (γ) values and check edge message (λ) values, and this by updating one or more individual rows within a number of sub-matrix rows (or all sub-matrix or sub-block rows) are processed in parallel. The amount of parallelism is specified by the designer and is typically an integer divisor of the sub-matrix (or sub-block) size.
1. An apparatus, comprising:
a first check module to update a first check edge message to generate an updated first check edge message;
a second check module to update a second check edge message to generate an updated second check edge message;
an APP (a posteriori probability) module to update an APP value, to generate an updated APP value, using a first difference between the first check edge message and the updated first check edge message and a second difference between the second check edge message and the updated second check edge message;
a daisy chain to store the updated APP value for use in a subsequent LDPC decoding iteration; and
a hard limiter to employ the updated APP value or a subsequently updated APP value to make an estimate of a bit encoded within an LDPC (Low Density Parity Check) coded signal.
2. The apparatus of claim 1 , wherein:
the APP module to update the APP value, to generate the updated APP value, using a plurality of differences, based on a plurality of check edge messages and a plurality of updated check edge messages, such that each difference of the plurality of differences is between a respective one check edge message of the plurality of check edge messages and a respective one updated check edge message of the plurality of updated check edge messages.
3. The apparatus of claim 1 , wherein the APP module including:
a first subtractor to calculate the first difference between the first check edge message and the updated first check edge message;
a second subtractor to calculate the second difference between the second check edge message and the updated second check edge message; and
an adder, connected to the first subtractor and the second subtractor, to update the APP value by adding the first difference and the second difference to the APP value.
4. The apparatus of claim 1 , wherein:
the APP (a posteriori probability) module is one of a plurality of APP modules;
the first check module and the second check module are two of a plurality of check modules; and
the plurality of APP modules and the plurality of APP modules operate cooperatively to process a plurality of sub-matrices of an LDPC matrix to make the estimate of the bit encoded within the LDPC coded signal.
5. The apparatus of claim 1 , wherein:
the apparatus being a communication device operative within at least one of a satellite communication system, a wireless communication system, a wired communication system, and a fiber-optic communication system.
6. An apparatus, comprising:
a first check module to update a first check edge message to generate an updated first check edge message;
a second check module to update a second check edge message to generate an updated second check edge message; and
an APP (a posteriori probability) module to update an APP value, to generate an updated APP value, using a first difference between the first check edge message and the updated first check edge message and a second difference between the second check edge message and the updated second check edge message; and wherein:
the apparatus to employ the updated APP value to make an estimate of a bit encoded within an LDPC (Low Density Parity Check) coded signal.
7. The apparatus of claim 6 , wherein:
the APP module to update the APP value, to generate the updated APP value, using a plurality of differences, based on a plurality of check edge messages and a plurality of updated check edge messages, such that each difference of the plurality of differences is between a respective one check edge message of the plurality of check edge messages and a respective one updated check edge message of the plurality of updated check edge messages.
8. The apparatus of claim 6 , wherein the APP module including:
a first subtractor to calculate the first difference between the first check edge message and the updated first check edge message;
a second subtractor to calculate the second difference between the second check edge message and the updated second check edge message; and
an adder, connected to the first subtractor and the second subtractor, to update the APP value by adding the first difference and the second difference to the APP value.
9. The apparatus of claim 6 , further comprising:
a daisy chain to store the updated APP value for use in a subsequent LDPC decoding iteration.
10. The apparatus of claim 6 , further comprising:
a hard limiter to process the updated APP value to make the estimate of the bit encoded within the LDPC coded signal.
11. The apparatus of claim 6 , wherein:
the APP (a posteriori probability) module is one of a plurality of APP modules;
the first check module and the second check module are two of a plurality of check modules; and
the plurality of APP modules and the plurality of APP modules operate cooperatively to process a plurality of sub-matrices of an LDPC matrix to make the estimate of the bit encoded within the LDPC coded signal.
12. The apparatus of claim 6 , wherein:
the first check module and the second check module implemented in at least one of a pipelined and a layered LDPC decoder architecture.
13. The apparatus of claim 6 , wherein:
the apparatus being a communication device operative within at least one of a satellite communication system, a wireless communication system, a wired communication system, and a fiber-optic communication system.
14. A method for operating a communication device, the method comprising:
operating a first check module to update a first check edge message to generate an updated first check edge message;
operating a second check module to update a second check edge message to generate an updated second check edge message;
operating an APP (a posteriori probability) module to update an APP value, to generate an updated APP value, using a first difference between the first check edge message and the updated first check edge message and a second difference between the second check edge message and the updated second check edge message; and
employing the updated APP value to make an estimate of a bit encoded within an LDPC (Low Density Parity Check) coded signal.
15. The method of claim 14 , further comprising:
operating the APP module to update the APP value, to generate the updated APP value, using a plurality of differences, based on a plurality of check edge messages and a plurality of updated check edge messages, such that each difference of the plurality of differences is between a respective one check edge message of the plurality of check edge messages and a respective one updated check edge message of the plurality of updated check edge messages.
16. The method of claim 14 , further comprising:
operating a first subtractor of the APP module to calculate the first difference between the first check edge message and the updated first check edge message;
operating a second subtractor of the APP module to calculate the second difference between the second check edge message and the updated second check edge message; and
operating an adder of the APP module, the adder connected to the first subtractor and the second subtractor, to update the APP value by adding the first difference and the second difference to the APP value.
17. The method of claim 14 , further comprising:
operating a hard limiter to process the updated APP value to make the estimate of the bit encoded within the LDPC coded signal.
18. The method of claim 14 , wherein:
the APP (a posteriori probability) module is one of a plurality of APP modules;
the first check module and the second check module are two of a plurality of check modules; and
the plurality of APP modules and the plurality of APP modules operate cooperatively to process a plurality of sub-matrices of an LDPC matrix to make the estimate of the bit encoded within the LDPC coded signal.
19. The method of claim 14 , wherein:
the first check module and the second check module implemented in at least one of a pipelined and a layered LDPC decoder architecture of the communication device.
20. The method of claim 14 , wherein:
the method performed within a communication device operative within at least one of a satellite communication system, a wireless communication system, a wired communication system, and a fiber-optic communication system.