Distributing clock associated with a wired data connection over wireless interfaces using frequency correction at the transmitter side
View Patent ↗A clock extractor extracts clock frequency f 2 , from a wired data connection feeding the transmitter with data clocked at the clock frequency f 2 . A clock error estimator estimates clock frequency error between the clock frequency f 2 and a clock frequency f 1 derived from a local clock of the transmitter. Clock adder adds the clock frequency error to the clock frequency f 1 , resulting in a synthesized clock frequency f 2 . A modulator uses the synthesized clock frequency f 2 , to modulate a data stream into a modulated signal.
1. A method for using a synthesized clock frequency to generate a modulated signal, comprising:
extracting, by a transmitter, clock frequency f 2 from a wired data connection feeding the transmitter with data clocked at the clock frequency f 2 ;
estimating clock frequency error between the clock frequency f 2 and a clock frequency f 1 derived from a local clock of the transmitter;
adding the clock frequency error to the clock frequency f 1 , resulting in a synthesized clock frequency f 2 ;
using the synthesized clock frequency f 2 to modulate a data stream into a modulated signal;
reconstructing, by a radio of a receiver, the synthesized clock frequency f 2 into reconstructed synthesized clock frequency f 2 ; and
clocking a second wired data connection, at the receiver, using the reconstructed synthesized clock frequency f 2 .
2. The method of claim 1 , wherein adding the clock frequency error to the clock frequency f 1 is done using Direct Digital Synthesis (DDS).
3. The method of claim 2 , wherein the DDS is a discrete component in the transmitter.
4. The method of claim 1 , wherein adding the clock frequency error to the clock frequency f 1 is done numerically by a processor.
5. The method of claim 4 , wherein the processor is also used to modulate the data.
6. The method of claim 4 , wherein adding the clock frequency error to the clock frequency f 1 is done using Direct Digital Synthesis (DDS).
7. The method of claim 1 , wherein the modulated signal is OFDM, and using the synthesized clock frequency f 2 to modulate the data comprises clocking an Inverse Fast Fourier Transform (IFFT) using a clock associated with the synthesized clock frequency f 2 .
8. The method of claim 1 , wherein estimating the clock frequency error between the clock frequency f 2 and the clock frequency f 1 is done by counting clock cycles of the clock frequency f 2 and the clock frequency f 1 over a period, and comparing the counts.
9. The method of claim 1 , further comprising the step of up-converting the modulated signal into a wireless signal containing the synthesized clock frequency f 2 .
10. The method of claim 1 , wherein the wired data connection feeding the transmitter is an Ethernet wired connection.
11. A method for using a synthesized clock frequency to generate a wireless signal, comprising:
extracting, by a transmitter, clock frequency f 2 from a wired data connection feeding the transmitter with data clocked at the clock frequency f 2 ;
estimating clock frequency error between the clock frequency f 2 and a clock frequency f 1 derived from a local clock of the transmitter;
adding the clock frequency error to the clock frequency f 1 , resulting in a synthesized clock frequency f 2 ;
modulating a data stream into a modulated signal;
up-converting, using the synthesized clock frequency f 2 , the modulated signal into a wireless signal;
reconstructing, by a radio of a receiver, from the wireless signal, the synthesized clock frequency f 2 into reconstructed synthesized clock frequency f 2 ; and
clocking a second wired data connection, at the receiver, using the reconstructed synthesized clock frequency f 2 .
12. The method of claim 11 , wherein adding the clock frequency error to the clock frequency f 1 is done using Direct Digital Synthesis (DDS).
13. The method of claim 12 , wherein the DDS is a discrete component in the transmitter.
14. The method of claim 11 , wherein adding the clock frequency error to the clock frequency f 1 is done numerically by a processor.
15. The method of claim 11 , wherein estimating the clock frequency error between the clock frequency f 2 and the clock frequency f 1 is done by counting clock cycles of the clock frequency f 2 and the clock frequency f 1 over a period, and comparing the counts.
16. The method of claim 11 , wherein the extraction is done using a Phase Lock Loop (PLL).
17. A method for using a synthesized clock frequency to generate a modulated signal and up-convert it to a wireless signal, comprising:
extracting, by a transmitter, clock frequency f 2 from a wired data connection feeding the transmitter with data clocked at the clock frequency f 2 ;
estimating clock frequency error between the clock frequency f 2 and a clock frequency f 1 derived from a local clock of the transmitter;
adding the clock frequency error to the clock frequency f 1 , resulting in a synthesized clock frequency f 2 ;
using the synthesized clock frequency f 2 to modulate a data stream into a modulated signal containing the synthesized clock frequency f 2 ;
up-converting, using the synthesized clock frequency f 2 , the modulated signal into a wireless signal containing synthesized clock frequency f 2 ;
reconstructing, by a radio of a receiver, from the wireless signal, the synthesized clock frequency f 2 into reconstructed synthesized clock frequency f 2 ; and
clocking a second wired data connection, at the receiver, using the reconstructed synthesized clock frequency f 2 .
18. The method of claim 17 , wherein the wired data connection feeding the transmitter is an Ethernet wired connection.