Multi-transistor exposed conductive clip for semiconductor packages
View Patent ↗One exemplary disclosed embodiment comprises a semiconductor package including multiple transistors coupled to an exposed conductive clip. A driver integrated circuit (IC) may control the transistors to implement a buck converter. By exposing a top surface of the exposed conductive clip outside of a mold compound of the package, enhanced thermal performance is provided. Additionally, the conductive clip provides a short distance, high current carrying route between transistors of the package, providing higher electrical performance and reduced form factor compared to conventional designs with individually packaged transistors.
1. A semiconductor package comprising:
at least two transistors including a control transistor having a control source on a top surface thereof and a sync transistor having a sync drain on a top surface thereof;
a driver integrated circuit (IC) coupled to said at least two transistors;
a single exposed conductive clip coupled directly to said control source and directly to said sync drain and directly to a pad in the semiconductor package.
2. The semiconductor package of claim 1 further comprising a mold compound enclosing said at least two transistors without covering a top surface of said exposed conductive clip.
3. The semiconductor package of claim 1 , wherein said driver IC is coupled to a sync gate of said sync transistor by at least one wirebond.
4. The semiconductor package of claim 1 , wherein said driver IC is coupled to a control gate of said control transistor by at least one wirebond.
5. The semiconductor package of claim 1 , wherein said driver IC is coupled to a sync gate of said syn transistor and to a control gate of said control transistor through respective wirebonds.
6. The semiconductor package of claim 1 , wherein said control transistor is a field effect transistor (FET).
7. The semiconductor package of claim 1 , wherein said sync transistor is a field effect transistor (FET).
8. The semiconductor package of claim 1 , wherein said driver IC is a flip chip.
9. The semiconductor package of claim 2 , wherein said mold compound encloses said driver IC without covering a top surface of said driver IC.
10. The semiconductor package of claim 1 , wherein said package comprises a buck converter.
11. The semiconductor package of claim 1 , wherein said exposed conductive clip is further attached to a leadframe pad of said package.
12. The semiconductor package of claim 1 , wherein said exposed conductive clip comprises a plurality of stacked clips.
13. The semiconductor package of claim 1 , wherein said package is a leadless package.
14. The semiconductor package of claim 1 , wherein said at least two transistors include a III-nitride transistor.
15. A semiconductor package comprising:
a control transistor including a top surface having a control gate and a control source;
a sync transistor including a top surface having a sync drain and a bottom surface including a sync gate;
a driver integrated circuit (IC) coupled to said control gate and said sync gate;
a single exposed conductive clip coupled directly to said control source and directly to said sync drain and directly to a pad in said semiconductor package.
16. The semiconductor package of claim 15 further comprising a mold compound enclosing said control transistor and said sync transistor without covering a top surface of said exposed conductive clip.
17. The semiconductor package of claim 15 , wherein said driver IC is coupled to said sync gate and to said control gate through respective wirebonds.
18. The semiconductor package of claim 15 , wherein said control transistor and said sync transistor are field effect transistors (FETs).
19. The semiconductor package of claim 15 , wherein said driver IC is a flip chip.
20. The semiconductor package of claim 15 , wherein said mold compound encloses said driver IC without covering a top surface of said driver IC.