Semiconductor device
View Patent ↗The present invention provides a semiconductor device that ensures both the breakdown voltage characteristic and specific on-resistance characteristic required for a high-voltage semiconductor device and that includes a gate over a substrate, a source region formed at one side of the gate, a drain region formed at the other side of the gate, and a plurality of device isolation films formed between the source region and the drain region, below the gate.
1. A semiconductor device comprising:
a gate formed over a substrate; a source region formed at one side of the gate;
a drain region formed at the other side of the gate; and a plurality of device isolation films formed between the source region and the drain region, wherein the plurality of device isolation films are formed below the gate and among the plurality of device isolation films, the device isolation film located closest to the drain region overlaps with a portion of the gate, wherein the device isolation film located closest to the drain region has the largest linewidth and depth among the plurality of device isolation films.
2. The semiconductor device of claim 1 , wherein the plurality of device isolation films have a linewidth thereof that decreases gradually in accordance with the direction from the drain region toward the source region.
3. The semiconductor device of claim 1 , wherein the plurality of device isolation films have a depth thereof that decreases gradually in accordance with the direction from the drain region toward the source region.
4. The semiconductor device of claim 1 , wherein the plurality of device isolation films comprise a structure formed by a shallow trench isolation (STI) process.
5. A semiconductor device comprising:
a second-conductivity-type deep well formed over a substrate;
a first-conductivity-type well formed in the second-conductivity-type deep well;
a gate formed over the substrate so as to partially overlap with the first-conductivity-type well;
a second-conductivity-type source region formed in the first-conductivity-type well, at one side of the gate;
a second-conductivity-type drain region in the second-conductivity-type deep well, at the other side of the gate; and
a plurality of device isolation films formed in the second-conductivity-type deep well, wherein the plurality of device isolation films are formed below the gate and among the plurality of device isolation films, the device isolation film located closest to the drain Legion overlaps with a portion of the gate, wherein the device isolation film located closest to the drain region has the largest linewidth and depth among the plurality of device isolation films.
6. The semiconductor device of claim 5 , wherein the plurality of device isolation films have a linewidth thereof that decreases gradually in accordance with the direction from the drain region toward the source region.
7. The semiconductor device of claim 5 , wherein the plurality of device isolation films have a depth thereof that decreases gradually in accordance with the direction from the drain region toward the source region.
8. The semiconductor device of claim 5 , wherein the plurality of device isolation films comprise a structure formed by a shallow trench isolation (STI) process.
9. The semiconductor device of claim 1 , wherein the plurality of device isolation films comprise a first device isolation film and a second device isolation film, and wherein the first device isolation film is formed between the source and the second device isolation film, and the second device isolation film is formed between the first device isolation film and the drain region.
10. The semiconductor device of claim 5 , wherein the plurality of device isolation films comprise a first device isolation film and a second device isolation film, and wherein the first device isolation film is formed between the source and the second device isolation film, and the second device isolation film is formed between the first device isolation film and the drain region.