Combination HEVC deblocker/SAO filter
View Patent ↗Systems and methods are provided that allow a deblocking filter and a sample adaptive offset (SAO) filter to be combined in a loop filter stage of a High Efficiency Video Coding (HEVC) decoder. In combining the deblocking filter and the SAO filter, an intermediate buffer may not be utilized, while still allowing for the deblocking filter and the SAO filter to operate substantially in parallel. The order of pixel processing and the parallelization of operation is such that the processing performed by the SAO filter need not hinder the processing performed by the deblocking filter within the loop filter stage. Additionally, and by combining the deblocking filter and the SAO filter without utilizing buffering therebetween, savings in space and cost in implementing the HEVC decoder may be realized.
1. A method, comprising:
in a pipeline processing circuitry comprising a single pipeline stage including a
combined deblocking filter and sample adaptive offset (SAO) filter;
receiving, at the combined deblocking filter and SAO filter, at least filter type information indicating a type of filter to be utilized by the deblocking filter and offset information indicating an offset to add to one or more pixels of a first group of pixels at a same stage time from a register buffer;
deblocking the first group of pixels associated with a first processing block of pixels at a deblocking filter;
transmitting the deblocked first group of pixels directly without buffering to a sample SAO filter;
filtering the deblocked first group of pixels at the SAO filter; and
outputting the filtered and deblocked first group of pixels.
2. The method of claim 1 , wherein the first processing block of pixels comprises a 32 pixel by 32 pixel square block.
3. The method of claim 1 , wherein the first group of pixels comprises a plurality of pixels left of a first vertical edge of the first processing block of pixels and a plurality of pixels right of the first vertical edge of the first processing block.
4. The method of claim 3 further comprising, and prior to transmitting the deblocked first group of pixels directly to the SAO filter:
continuing deblocking subsequent groups of pixels associated with the first processing block until an entirety of the first vertical edge of the first processing block of pixels has been deblocked; and
continuing deblocking further subsequent groups of pixels associated with the first processing block of pixels, wherein further subsequent groups of pixels comprise a plurality of pixels above and a plurality of pixels below a first horizontal edge of the first processing block of pixels crossing the first vertical edge of the first processing block of pixels.
5. The method of claim 1 , wherein the deblocking at the deblocking filter and the filtering at the SAO filter occur substantially in parallel.
6. The method of claim 1 , where the filtering of the deblocked first group of pixels comprises determining, at the SAO filter, whether to add one of a plurality of offsets to one or more pixels of the first group of pixels.
7. The method of claim 6 further comprising, adding the one of the plurality of offsets to the one or more pixels if necessary.
8. The method of claim 1 , wherein the first group of pixels comprises a plurality of pixels left of a first vertical edge of the first processing block of pixels and a plurality of pixels right of the first vertical edge of the first processing block.
9. The method of claim 1 , wherein the deblocking filter is in communication with a first line buffer and the SAO filter is in communication with a second line buffer.
10. A computer program product, stored on a non- transitory computer-readable medium, comprising:
computer code for receiving at a loop filter stage of pipeline processing circuitry of a video decoder, a reconstructed video signal divided into at least one processing block from a first pipeline stage;
computer code for reading from a register buffer load information for controlling a combination deblocking and SAO filter at a same stage time, wherein the load information including at least filter type information indicating a type of filter to be utilized by the deblocking filter and offset information indicating an offset to add to one or more pixels of a first group of pixels;
computer code for performing substantially in parallel, deblocking filtering and sample adaptive offset (SAO) filtering on the processing block, wherein the at least one processing block is provided directly from the deblocking filtering without buffering to the SAO filtering; and
computer code for sending filtered pixels making up the at least one processing block to an output stage.
11. The computer program product of claim 10 , wherein the computer code for performing the deblocking filtering and SAO filtering substantially in parallel comprises computer code for passing output data from a deblocking filter performing the deblocking filtering directly to an SAO filter performing the SAO filtering.
12. The computer program product of claim 10 , wherein the computer code for performing the deblocking filtering and SAO filtering comprises computer code for performing the deblocking filtering at a deblocking filter in a processing order such that a first vertical edge of the processing block is completely deblocked prior to deblocking a first portion of a first horizontal edge crossing the first vertical edge.
13. The computer program product of claim 10 , wherein the computer code for performing the deblocking filtering and SAO filtering comprises computer code for performing SAO filtering at an SAO filter by determining whether to add one of a plurality of offsets to one or more pixels of the processing block, and adding the one of the plurality of offsets to the one or more pixels of the processing block if necessary.
14. The computer program product of claim 13 , wherein the computer code for performing the SAO filtering at the SAO filter comprises computer code for operating the SAO filter at an SAO filter operating rate matching a deblocking filter operating rate of a deblocking filter at which the deblocking filtering is performed.
15. The computer program product of claim 14 , wherein the SAO filter operating rate and the deblocking filter operating rate comprises a rate of four pixels per clock cycle.
16. A system comprising,
a pipeline processing circuitry comprising a single pipeline stage including a combination deblocking and sample adaptive offset (SAO) filter for deblocking a first group of pixels associated with a first processing block of pixels and adding an offset value to one or more pixels of the first group of pixels, wherein a deblocking filter portion of the combination deblocking and SAO filter passes output data directly without buffering to a SAO filter portion of the combination deblocking and SAO filter;
a register buffer for holding register load information for controlling the combination deblocking and SAO filter at a same stage time, wherein the load information including at least filter type information indicating a type of filter to be utilized by the deblocking filter and offset information indicating an offset to add to one or more pixels of the first group of pixels; and
at least one pixel buffer for, in conjunction with the register buffer, decoupling the system from additional stages of a video decoder.
17. The system of claim 16 , wherein the register load information comprises at least filter type information indicating a type of filter to be utilized by the deblocking filter portion of the combination deblocking and SAO filter, and offset information indicating the offset value to add to the one or more pixels of the first group of pixels.
18. The system of claim 16 , wherein the deblocking of the first group of pixels occurs substantially in parallel with the addition of the offset value to the one or more pixels of the first group of pixels.
19. The system of claim 16 , wherein the deblocking filter portion is in communication with a first line buffer and the SAO filter portion is in communication with a second line buffer.