Multi-port, gigabit SERDES transceiver capable of automatic fail switchover
View Patent ↗A multi-port Serdes transceiver includes multiple parallel ports and serial ports, and includes the flexibility to connect any of the parallel ports to another parallel port or to a serial port, or both. The transceiver can connect any of the serial ports to another serial port or to a parallel port. The transceiver includes a switch, a logic core, and a bus. The switch is selectively coupled to at least a first port and a second port. The switch activates the first port and deactivates the second port based on satisfaction of a condition associated with the first port. The logic core operates the serial and parallel ports, and the bus connects the ports. The bus can be described as a “ring” structure around the logic core, and is configured between the logic core and the ports. The ring structure provides efficient communication between the logic core and the ports.
1. A transceiver, comprising:
a first port configured to transmit and to receive data over a first plurality of lanes;
a second port configured to transmit and to receive the data over a second plurality of lanes; and
a switch selectively coupled to the first port and the second port;
wherein the switch is configured to activate the second port and to deactivate the first port when:
the data at a first lane from among the first plurality of lanes is misaligned, or
a number of errors at a second lane from among the first plurality of lanes exceeds a threshold, and
wherein the switch is further configured to begin its determination of whether the data at the first lane is misaligned substantially simultaneously with its determination of whether the number of errors at the second lane exceeds the threshold.
2. The transceiver of claim 1 , wherein a failure associated with the first port is indicated when the number of errors at the second lane exceeds the threshold.
3. The transceiver of claim 1 , wherein the switch is further configured to enable the data to be read at the second port and to disable the data from being read at the first port.
4. The transceiver of claim 1 , wherein the switch is further configured to enable the data to be transmitted at the second port and to disable the data from being transmitted at the first port.
5. The transceiver of claim 1 , wherein the first lane and the second lane represent a single lane from among the first plurality of lanes.
6. The transceiver of claim 1 , wherein the switch is further configured to determine that the data at the first lane is misaligned by detecting a byte alignment character in an unexpected location within the data at the first lane, the byte alignment character being periodically included within the data at one or more expected locations.
7. The transceiver of claim 6 , wherein the byte alignment character comprises:
a comma character.
8. A transceiver, comprising:
a first port configured to transmit and to receive data over a first plurality of lanes;
a second port configured to transmit and to receive the data over a second plurality of lanes; and
a switch selectively coupled to the first port and the second port;
wherein the switch is configured to activate the second port and to deactivate the first port when;
a number of errors at a first lane from among the first plurality of lanes exceeds a threshold, or
the data at a second lane from among the first plurality of lanes is misaligned with the data at other lanes from among the first plurality of lanes, and
wherein the switch is further configured to begin its determination of whether the number of errors at the first lane exceeds the threshold substantially simultaneously with its determination of whether the data at the second lane is misaligned with the data at the other lanes.
9. The transceiver of claim 8 , wherein a failure associated with the first port is indicated when the number of errors at the first lane exceeds the threshold.
10. The transceiver of claim 8 , wherein the switch is further configured to enable the data to be read at the second port and to disable the data from being read at the first port.
11. The transceiver of claim 8 , wherein the switch is further configured to enable the data to be transmitted at the second port and to disable the data from being transmitted at the first port.
12. The transceiver of claim 8 , wherein the first lane and the second lane represent a single lane from among the first plurality of lanes.
13. The transceiver of claim 8 , wherein the switch is further configured to electrically couple a third port to the first port or to the second port.
14. The transceiver of claim 13 , wherein the third port is a parallel port.
15. A transceiver, comprising:
a first port configured to transmit and to receive data over a first plurality of lanes;
a second port configured to transmit and to receive the data over a second plurality of lanes; and
a switch selectively coupled to the first port and the second port;
wherein the switch is configured to activate the second port and to deactivate the first port when:
the data at a first lane from among the first plurality of lanes is misaligned, or
the data at a second lane from among the first plurality of lanes is misaligned with the data at other lanes from among the first plurality of lanes, and
wherein the switch is further configured to begin its determination of whether the data at the first lane is misaligned substantially simultaneously with its determination of whether the data at the second lane is misaligned with the data at the other lanes.
16. The transceiver of claim 15 , wherein the switch is further configured to enable the data to be read at the second port and to disable the data from being read at the first port.
17. The transceiver of claim 15 , wherein the switch is further configured to enable the data to be transmitted at the second port and to disable the data from being transmitted at the first port.
18. The transceiver of claim 15 , wherein the switch is further configured to determine that the data at the first lane is misaligned by detecting a byte alignment character in an unexpected location within the data at the first lane, the byte alignment character being periodically included within the data at one or more expected locations.
19. The transceiver of claim 18 , wherein the byte alignment character comprises:
a comma character.
20. The transceiver of claim 15 , wherein the switch is further configured to electrically couple a third port to the first port or the second port.