Semiconductor device

1. A semiconductor system comprising:

a host device including a CPU; and

a semiconductor device; wherein the semiconductor device comprises:

a substrate comprising a multi-layer structure with a wiring pattern, and comprising a substantially rectangular shape in a plan view;

a connector to be connectable to the host device;

a volatile semiconductor memory element provided on a front surface layer side of the substrate;

a first nonvolatile semiconductor memory element provided on the front surface layer side of the substrate;

a second nonvolatile semiconductor memory element provided on the front surface layer side of the substrate;

a third nonvolatile semiconductor memory element provided on the front surface layer side of the substrate; and

a controller provided on the front surface layer side of the substrate to control the volatile semiconductor memory element and the nonvolatile semiconductor memory elements,

wherein the wiring pattern includes a signal line formed between the connector and the controller to connect the connector to the controller, and

wherein the first nonvolatile semiconductor memory element and the second nonvolatile semiconductor memory element are aligned along the longitudinal direction of the substrate, on the opposite side of the controller to the third nonvolatile semiconductor memory element,

wherein the CPU writes information on the first nonvolatile semiconductor memory element and the second nonvolatile semiconductor memory element through the connector.

2. A semiconductor system comprising:

a host device including a CPU; and

a semiconductor device; wherein the semiconductor device comprises:

a substrate comprising a multi-layer structure with a wiring pattern, and comprising a substantially rectangular shape in a plan view;

a connector provided on a short side of the substrate to be connectable to the host device;

a volatile semiconductor memory element provided on a front surface layer side of the substrate;

a first nonvolatile semiconductor memory element provided on the front surface layer side of the substrate;

a second nonvolatile semiconductor memory element provided on the front surface layer side of the substrate; and

a controller provided on the front surface layer side of the substrate to control the volatile semiconductor memory element and the nonvolatile semiconductor memory elements,

wherein the wiring pattern includes a signal line formed between the connector and the controller to connect the connector to the controller,

wherein the first nonvolatile semiconductor memory element and the second nonvolatile semiconductor memory element and the controller are aligned along the longitudinal direction of the substrate, and

wherein the controller between the first nonvolatile semiconductor memory element and the second nonvolatile semiconductor memory element,

wherein the CPU writes information on the first nonvolatile semiconductor memory element and the second nonvolatile semiconductor memory element through the connector.

3. The semiconductor system according to claim 2 , further comprising:

resistive elements provided on the front surface layer side of the substrate,

wherein the resistive elements are provided on wiring lines connecting the first and second nonvolatile semiconductor memory elements to the controller, and are disposed near the nonvolatile semiconductor memory elements.

4. The semiconductor system according to claim 2 ,

wherein the first and second nonvolatile semiconductor memory elements are disposed on one long side of the substrate.

5. The semiconductor system according to claim 2 ,

wherein the first nonvolatile semiconductor memory element is disposed on one long side of the substrate and the second nonvolatile semiconductor memory element is disposed on the other long side of the substrate.

6. The semiconductor system according to claim 2 ,

wherein the wiring pattern is formed to bypass a region overlapping the signal line.

7. The semiconductor system according to claim 6 ,

wherein the signal line is formed in a front surface layer of the substrate.

8. The semiconductor system according to claim 2 ,

wherein the volatile semiconductor memory element is disposed between the connector and the controller.

9. The semiconductor system according to claim 2 ,

wherein the signal line extends over the front surface layer of the substrate from the controller to a vicinity of the connector, passes through the substrate up to a rear surface layer of the substrate at a position near the connector, and extends over the rear surface layer to be connected to the connector.

10. The semiconductor system according to claim 2 ,

wherein almost an entire region of the rear surface layer of the substrate is a ground.

11. The semiconductor system according to claim 2 ,

wherein the first nonvolatile semiconductor memory element or the second nonvolatile semiconductor memory element is disposed between the controller and the connector.

12. The semiconductor system according to claim 11 ,

wherein the signal line is formed in an inside layer of the substrate.

13. The semiconductor system according to claim 2 , further comprising:

a third nonvolatile semiconductor memory element provided on a rear surface layer side of the substrate.

14. The semiconductor system according to claim 2 ,

wherein the first and second nonvolatile semiconductor memory elements are NAND flash memories.

15. The semiconductor system according to claim 2 ,

wherein the volatile semiconductor memory element is a DRAM.

16. The semiconductor system according to claim 2 ,

wherein the connector includes a slit formed at a position deviating from a center of the substrate in a direction of a short side of the substrate.

17. The semiconductor system according to claim 2 ,

wherein the connector is a LIF connector.

18. The semiconductor system according to claim 2 , further comprising:

a power supply circuit provided on the front surface layer of the substrate,

wherein the power supply circuit is disposed near the connector.