IP Library Granted Patent US 8,661,318
Granted Patent B2
US 8,661,318 · App. 13/732,808 · Granted Feb 25, 2014

Memory management in a non-volatile solid state memory device

Inventors: Evangelos S Eleftheriou (Zurich, CH); Ilias Iliadis (Zurich, CH); Robert Haas (Zurich, CH); Xiaoyu Hu (Zurich, CH)
Assignee: International Business Machines Corporation
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Quick Facts
Patent No.
US 8,661,318
App. No.
13/732,808
Granted
Feb 25, 2014
Kind
B2
Abstract

A computer-implemented method of managing a memory of a non-volatile solid state memory device by balancing write/erase cycles among blocks to level block usage. The method includes monitoring an occurrence of an error during a read operation in a memory unit of the device, where the error is correctable by error-correcting code, and programming the memory unit according to the monitored occurrence of the error, where the step of monitoring the occurrence of an error is carried out for at least one block, and wherein said step of programming includes wear-leveling the monitored block according the error monitored for the monitored block.

Claims (18)

1. A computer-implemented method of managing a memory of a non-volatile solid state memory device by balancing write/erase cycles among blocks to level block usage, said method comprising:

reserving a subset of the blocks for future data migration, the reserved subset of blocks being deemed writable;

monitoring a plurality of read operations on the blocks of the memory unit of said device;

detecting one or more errors resulting from the read operations, wherein said errors are correctable by error-correcting code; and

programming said memory unit according to said errors, wherein the programming comprises wear-leveling the monitored block according the errors detected in the monitored blocks, and wherein the wear-leveling excludes the reserved subset of blocks; and

migrating data from at least one of the monitored blocks to at least one of the reserved subset of blocks.

2. The method according to claim 1 , further comprising determining a change in a measure of the errors between a first cycle and a second cycle, wherein programming said memory unit according to said errors comprises programming the memory unit according to the change in the errors.

3. The method according to claim 1 , wherein said memory unit subdivides into dice, each said die comprising at least one block, and wherein detecting the errors is carried out for each said blocks of the dice.

4. The method according to claim 2 , wherein monitoring the plurality of read operations on the blocks comprises monitoring a first set of consecutive read operations, and wherein determining the change in the measure of the errors comprises determining the change in the errors between the first set of consecutive read operations and a second set of consecutive read operations.

5. The method according to claim 1 , further comprising:

maintaining a per-block counter of write-erase data, and

wherein programming said memory is carried out according to both said errors detected and said write-erase data maintained.

6. The method according to claim 1 , wherein said memory unit subdivides into dice, each said die comprising at least one block.

7. The method according to claim 1 , wherein reserving the reserved subset of blocks is performed independent of the number of said errors detected or the number of write-erase operations performed in each of said blocks of said memory unit.

8. The method according to claim 1 , wherein the quantity of blocks in the reserved subset of blocks is decided or refined based on the number of said errors detected or said write-erase data maintained.

9. The method according to claim 6 ,

wherein migrating data from at least one of the monitored blocks to at least one of the reserved subset of blocks is performed if a rate of errors exceeds a threshold indicative of a depletion of writable memory space in said memory unit.

10. An article of manufacture tangibly embodying computer readable instructions which when implemented, causes said computerized system to carry out the method of managing a memory of a non-volatile solid state memory device according to claim 1 .

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 25, 2014
From: INTERNATIONAL BUSINESS MACHINES CORPORATION
To: SK HYNIX INC.
Reel/Frame 033417/0880 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 27, 2013
From: ELEFTHERIOU, EVANGELOS S; ILIADIS, ILIAS; HAAS, ROBERT; HU, XIAOYU
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 030095/0345 →
Priority Claims (1)
EP 09166231 · Jul 23, 2009 · regional
Continuity (2)
Continuation 12835783 · Jul 14, 2010
Related Publication 20130117600A1 · May 9, 2013