IP Library Granted Patent US 8,547,740
Granted Patent B2
US 8,547,740 · App. 13/734,335 · Granted Oct 1, 2013

Adaptive estimation of memory cell read thresholds

Inventors: Naftali Sommer (Rishon Le-Zion, IL); Ofir Shalvi (Ra'anana, IL); Uri Perlmutter (Ra'anana, IL); Oren Golov (Hod-Hasharon, IL); Eyal Gurgi (Petah-Tikva, IL); Micha Anholt (Tel Aviv, IL); Dotan Sokolov (Ra'anana, IL)
Assignee: Apple Inc.
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 8,547,740
App. No.
13/734,335
Granted
Oct 1, 2013
Kind
B2
Abstract

A method for operating a memory ( 28 ) that includes a plurality of analog memory cells ( 32 ) includes storing data in the memory by writing first storage values to the cells. Second storage values are read from the cells, and a Cumulative Distribution Function (CDF) of the second storage values is estimated. The estimated CDF is processed so as to compute one or more thresholds. A memory access operation is performed on the cells using the one or more thresholds.

Claims (50)

1. A method, comprising:

receiving data to be stored in a memory, wherein the memory includes a plurality of data storage cells;

writing first storage values in the plurality of data storage cells;

reading second storage values from the plurality of data storage cells;

determining a number of data memory cells of the plurality of data memory cells associated with a plurality of programming levels dependent upon the read second storage values;

estimating a probability density function (PDF) for each programming level of the plurality of programming levels;

scaling each PDF dependent upon the determined number of data storage cells;

integrating the plurality of PDFs to produce a cumulative distribution function (CDF);

computing one or more thresholds dependent upon the CDF;

reading third storage values from the plurality of data storage cells;

comparing the third storage values to the computed one or more thresholds; and

generating data bits dependent upon the comparison.

2. The method of claim 1 , wherein each data storage cell of the plurality of data storage cells comprises an analog memory cell.

3. The method of claim 1 , wherein each data storage cell of the plurality of data storage cells comprises a multi-bit analog memory cell.

4. The method of claim 1 , wherein reading second storage values comprises converting an electrical charge into digital samples.

5. The method of claim 1 , wherein writing first storage values comprises encoding the received data using an error correction code (ECC).

6. An apparatus, comprising:

a memory including a plurality of data storage cells; and

a controller coupled to the memory, wherein the controller is configured to:

receive data to be stored in the memory;

write first storage values in the plurality of data storage cells;

read second storage values from the plurality of data storage cells;

determine a number of data storage cells of the plurality of data storage cells associated with a plurality of programming levels dependent upon the read second storage values;

estimate a probability density function (PDF) for each programming level of the plurality of programming levels;

scale each PDF dependent upon the determined number of data storage cells;

integrate the plurality of PDFs to produce a cumulative distribution function (CDF);

compute one or more thresholds dependent upon the CDF;

read third storage values from the plurality of data storage cells;

compare the third storage values to the computed one or more thresholds; and

generate data bits dependent upon the comparison.

7. The apparatus of claim 6 , wherein each data cell of the plurality of data storage cells comprises an analog memory cell.

8. The apparatus of claim 6 , wherein read second storage values comprises converting an electrical charge into digital samples.

9. The apparatus of claim 6 , wherein write first storage values in the plurality of data storage cells comprises encoding the data using an error correction code (ECC).

10. The apparatus of claim 9 , wherein the controller is further configured to decode the data bits using the ECC.

11. A non-transitory computer accessible storage medium having program instructions stored therein that, in response to execution by a computer system, causes the computer system to perform operations including:

receiving data to be stored in a memory, wherein the memory includes a plurality of data storage cells;

writing first storage values in the plurality of data storage cells;

reading second storage values from the plurality of data storage cells;

determining a number of data storage cells of the plurality of memory cells associated with a plurality of programming levels dependent upon the read second storage values;

estimating a probability density function (PDF) for each programming level of the plurality of programming levels;

scaling each PDF dependent upon the determined number of data storage cells;

integrating the plurality of PDFs to produce a cumulative distribution function (CDF);

computing one or more thresholds dependent upon the CDF;

reading third storage values from the plurality of data storage cells;

comparing the third storage values to the computed one or more thresholds; and

generating data bits dependent upon the comparison.

12. The non-transitory computer accessible storage medium of claim 11 , wherein each data storage cell of the plurality of data storage cells comprises an multi-bit analog memory cell.

13. The non-transitory computer accessible storage medium of claim 11 , wherein the writing the first storage values comprises encoding the data with an error correction code (ECC).

14. The non-transitory computer accessible storage medium of claim 13 , wherein perform operations further includes decoding the data bits using the ECC.

15. The non-transitory computer accessible storage medium of claim 13 , wherein the ECC comprises a low density parity check (LDPC).

Continuity (5)
Continuation 12522175
Provisional Application 60894290 · Mar 12, 2007
Provisional Application 61016824 · Dec 27, 2007
Provisional Application 61017177 · Dec 28, 2007
Related Publication 20130121080A1 · May 16, 2013