Buffer circuit and buffer circuit driving method

1. A buffer circuit driving method for driving a buffer circuit including: an output terminal; a first transistor connected to a signal source of a clock signal that is of at least a first voltage or a second voltage lower than the first voltage, for supplying the first voltage to the output terminal; and a second transistor connected to a voltage source that supplies a third voltage lower than the first voltage, for supplying the third voltage to the output terminal, the buffer circuit driving method comprising:

causing the first transistor to switch to a conducting state in a period in which the clock signal is of the first voltage; and

causing both the first transistor and the second transistor to switch to the conducting state in a period in which the clock signal is of the second voltage, following the period in which the clock signal is of the first voltage,

wherein a period in which both the first transistor and the second transistor are in the conducting state is a half cycle of the clock signal.

2. The buffer circuit driving method according to claim 1 , wherein the output terminal outputs the second voltage in a period in which both the first transistor and the second transistor are in the conducting state.

3. The buffer circuit driving method according to claim 1 , wherein the buffer circuit is provided in a scanning line driving circuit that generates a driving signal for scanning lines of a display, and

a signal of the first voltage, the second voltage and the third voltage output from the output terminal is supplied to the display as the driving signal, but is not supplied to the scanning line driving circuit.

4. The buffer driving method according to claim 3 , wherein the buffer circuit further includes a second output terminal separately from the output terminal, and the second output terminal outputs a signal only to the scanning line driving circuit.

5. The buffer driving method according to claim 1 , wherein the second voltage is set lower than the third voltage, and

the output terminal outputs the first voltage, the second voltage and the third voltage.

6. A buffer circuit comprising:

an output terminal;

a first transistor connected to a signal source of a clock signal that is of at least a first voltage or a second voltage lower than the first voltage, for supplying the first voltage to the output terminal; and

a second transistor connected to a voltage source that supplies a third voltage lower than the first voltage, for supplying the third voltage to the output terminal,

wherein the first transistor is caused to switch to a conducting state in a period in which the clock signal is of the first voltage, and

both the first transistor and the second transistor are caused to switch to the conducting state in a period in which the clock signal is of the second voltage, following the period in which the clock signal is of the first voltage, and

a period in which both the first transistor and the second transistor are in the conducting state is a half cycle of the clock signal.

7. The buffer circuit according to claim 6 ,

wherein the first transistor has a gate connected to the output terminal via a capacitor element.

8. A shift register comprising unit circuits connected in multiple stages and each including a logic circuit and an output including the buffer circuit according to claim 6 ,

wherein the logic circuit includes:

a first signal generator configured to generate, according to a signal input from one of the unit circuits which is in an immediately preceding stage, a first signal for switching the first transistor between the conducting state and a non-conducting state; and

a second signal generator configured to generate a second signal for switching the second transistor between the conducting state and the non-conducting state.

9. The buffer circuit according to claim 6 ,

wherein the first transistor and the second transistor have depression characteristics.

10. The buffer circuit according to claim 6 , wherein the output terminal outputs the second voltage in a period in which both the first transistor and the second transistor are in the conducting state.

11. The buffer circuit according to claim 6 , wherein the buffer circuit is provided in a scanning line driving circuit that generates a driving signal for scanning lines of a display, and

a signal of the first voltage, the second voltage and the third voltage output from the output terminal is supplied to the display as the driving signal, but is not supplied to the scanning line driving circuit.

12. The buffer circuit according to claim 11 , wherein the buffer circuit further includes a second output terminal separately from the output terminal, and the second output terminal outputs a signal only to the scanning line driving circuit.