Semiconductor apparatus
View Patent ↗A semiconductor apparatus includes: a sense amplifier unit enabled for a predetermined time during a read operation in response to a first read enable signal, enabled before a write operation in response to a second read enable signal, and disabled when the write operation is started, and a switch unit configured to connect a write driver and a memory unit during the write operation in response to a first select signal, connect the sense amplifier unit and the memory unit for the predetermined time during the read operation in response to a control signal, and disconnect the sense amplifier and the memory unit when the write operation is started.
1. A semiconductor apparatus comprising:
a sense amplifier unit enabled for a predetermined time during a read operation in response to a first read enable signal, enabled before a write operation in response to a second read enable signal, and disabled when the write operation is started;
a switch unit configured to connect a write driver and a memory unit during the write operation in response to a first select signal, connect the sense amplifier unit and the memory unit for the predetermined time during the read operation in response to a control signal, and disconnect the sense amplifier and the memory unit when the write operation is started, and
a control unit configured to generate the control signal and the second read enable signal in response to the first read enable signal and a second select signal.
2. The semiconductor apparatus according to claim 1 , wherein the control unit generates the second read enable signal by delaying the first read enable signal.
3. The semiconductor apparatus according to claim 2 , wherein the first select signal comprises a signal enabled during a write operation.
4. The semiconductor apparatus according to claim 3 , wherein the second select signal comprises a signal enabled during a read operation.
5. The semiconductor apparatus according to claim 4 , wherein the control unit performs a logic operation on the second read enable signal and the second select signal, and outputs the control signal.
6. The semiconductor apparatus according to claim 2 , wherein the sense amplifier unit comprises:
a signal combination section configured to perform a logic operation on the first and second read enable signals; and
a sense amplifier connected to the memory unit in response to an output signal of the signal combination section.
7. The semiconductor apparatus according to claim 1 , wherein the memory unit comprises a phase change memory element.
8. The semiconductor apparatus according to claim 1 , wherein the sense amplifier unit comprises:
a signal combination section configured to perform a logic operation on the first and second read enable signals; and
a sense amplifier connected to the memory unit in response to an output signal of the signal combination section.
9. The semiconductor apparatus according to claim 8 , wherein the memory unit comprises a phase change memory element.
10. A semiconductor apparatus comprising:
a switch unit configured to control a first current path where a write driver and a memory unit are connected during a write operation in response to a first select signal and a control signal and control a second current path where a sense amplifier unit and the memory unit are connected for a predetermined time during a read operation and then disconnected when the write operation is started; and
a control unit configured to output the control signal in response to a first read enable signal and a second select signal,
wherein the control unit generates the second read enable signal by delaying the first read enable signal.
11. The semiconductor apparatus according to claim 10 , wherein the first select signal comprises a signal enabled during a write operation.
12. The semiconductor apparatus according to claim 11 , wherein the second select signal comprises a signal enabled during a read operation.
13. The semiconductor apparatus according to claim 12 , wherein the control unit performs a logic operation on the second read enable signal and the second select signal, and outputs the control signal.