IP Library Granted Patent US 9,042,150
Granted Patent B2
US 9,042,150 · App. 13/737,321 · Granted May 26, 2015

Programmable and flexible reference cell selection method for memory devices

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Quick Facts
Patent No.
US 9,042,150
App. No.
13/737,321
Granted
May 26, 2015
Kind
B2
Abstract

An exemplary system includes an array of interconnected cells and a flexible decoder. The array is configured to receive a selection signal as input, select a cell based upon the selection signal, and provide an output based on the selected cell. The flexible decoder is configured to receive an input, generate a selection signal based on the input and one or more characteristics of the array of interconnected cells, and provide the selection signal to the array of interconnected cells.

Claims (73)

1. A system, comprising:

an array of interconnected cells configured to:

receive a selection signal as input;

select a cell based upon the selection signal; and

provide an output based upon the selected cell; and

a flexible decoder comprising:

a memory storing programming instructions, wherein the programming instructions correlate any input to any selection signal; and

wherein the flexible decoder is configured to:

receive an input;

determine the selection signal based on the input and one or more characteristics of the array of interconnected cells by executing the programming instructions; and

provide the selection signal to the array of interconnected cells.

2. The system of claim 1 , wherein the array of interconnected cells includes a reference array of reference sources; and

wherein the output is a reference current or voltage.

3. The system of claim 1 , wherein the array of interconnected cells includes an array of sensor cells; and

wherein the output is output from a sensor cell.

4. The system of claim 1 , wherein the program instructions and processor are configured to receive input in the form of a detectable environmental condition.

5. The system of claim 2 , further comprising:

a memory array of interconnected memory cells; and

at least one comparator configured to:

receive a signal from the reference array and a signal from the memory array; and

determine the state of at least one memory cell by comparing the signals from the reference array and the memory array.

6. The system of claim 5 , wherein the flexible decoder is further configured to:

provide signals to the memory array and the reference array so as to perform at least one of the following operations on the memory array: read, program/write, and erase.

7. The system of claim 5 , wherein the flexible decoder is further configured to:

receive input in the form of a detectable environmental condition; and

perform at least one of the following operations on the memory array based on the received input: read, program/write, and erase.

8. The system of claim 5 , wherein the flexible decoder is further configured to:

perform periodic monitoring of the memory array to detect errors; and

perform refresh operations to correct errors.

9. A method of conditioning a reference array, comprising:

receiving an input;

generating a selection signal, based on the input and one or more characteristics of a reference array of interconnected reference sources;

correlating the generated selection signal with the input in one or more programming instructions, wherein the programming instructions correlate any input to any selection signal;

providing the selection signal to the reference array, wherein the reference array provides a reference current or voltage as output corresponding to the selection signal;

repeating the receiving, generating, and providing steps for a plurality of inputs to determine a relationship between the inputs and their respective output currents or voltages; and

changing the generation of selection signals so as to change the relationship between the plurality of inputs and their respective output currents or voltages.

10. The method of claim 7 , further comprising:

receiving input in the form of a detectable environmental condition.

11. A method, comprising:

receiving an input;

generating a selection signal by executing programming instructions based on the input and one or more characteristics of a reference array of interconnected reference sources, wherein the programming instructions correlate any input to any selection signal; and

providing the selection signal to the reference array, wherein the reference array provides a reference current or voltage as output corresponding to the selection signal.

12. The method of claim 11 , further comprising:

receiving input in the form of a detectable environmental condition.

13. The method of claim 11 , further comprising:

generating and providing an input signal to a memory array of interconnected memory cells;

receiving an output signal from the memory array; and

determining the state of at least one memory cell by comparing the output signal from the reference array with the reference current or voltage from the reference array.

14. The method of claim 13 , further comprising:

providing signals to the memory array and reference array so as to perform at least one of the following operations on the memory array: read, program/write, and erase.

15. The method of claim 13 , further comprising:

receiving input in the form of a detectable environmental condition; and

performing one of the following operations on the memory array based on the received input: read, program/write, and erase.

16. The method of claim 13 , further comprising:

performing periodic monitoring of the memory array to detect errors; and

performing refresh operations to correct errors.

17. A non-transitory computer readable storage medium having program instructions stored thereon that, when executed by a processor, cause the processor to perform operations, the operations comprising:

receiving an input;

generating a selection signal by executing programming instructions based on the input and one or more characteristics of a reference array of interconnected reference sources, wherein the programming instructions correlate any input to any selection signal; and

providing the selection signal to a reference array of interconnected reference sources to cause the array to provide a reference current or voltage as output.

18. The computer readable storage medium of claim 17 , wherein the operations further comprise:

receiving input in the form of a detectable environmental condition.

19. The computer readable storage medium of claim 17 , wherein the operations further comprise:

generating and providing an input signal to a memory array of interconnected memory cells; receiving an output signal from the memory array; and

determining the state of at least one memory cell by comparing the output signal from the reference array with the reference current or voltage from the reference array.

20. The computer readable storage medium of claim 17 , wherein the operations further comprise:

providing signals to the memory array and reference array so as to perform at least one of the following operations on the memory array: read, program/write, and erase.

21. The computer readable storage medium of claim 19 , wherein the operations further comprise:

receiving input in the form of a detectable environmental condition; and

performing at least one of the following operations on the memory array based on the received input: read, program/write, and erase.

22. The computer readable storage medium of claim 19 , wherein the operations further comprise:

performing periodic monitoring of the memory array to detect errors; and

performing refresh operations to correct errors.

Assignments (7)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 15, 2022
From: CYPRESS SEMICONDUCTOR CORPORATION
To: INFINEON TECHNOLOGIES LLC
Reel/Frame 059721/0467 →
RELEASE OF SECURITY INTEREST Recorded Mar 16, 2022
From: MUFG UNION BANK, N.A.
To: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
Reel/Frame 059410/0438 →
CORRECTIVE ASSIGNMENT TO CORRECT THE 8647899 PREVIOUSLY RECORDED ON REEL 035240 FRAME 0429. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTERST. Recorded Nov 3, 2020
From: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 058002/0470 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN INTELLECTUAL PROPERTY Recorded Oct 28, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: MUFG UNION BANK, N.A.
Reel/Frame 050896/0366 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 9, 2015
From: SPANSION LLC
To: CYPRESS SEMICONDUCTOR CORPORATION
Reel/Frame 035872/0344 →
SECURITY INTEREST Recorded Mar 21, 2015
From: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 035240/0429 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 9, 2013
From: ACHTER, MICHAEL; BINBOGA, EVRIM; KUO, HARRY
To: SPANSION LLC
Reel/Frame 029599/0506 →