Timing generation circuit
View Patent ↗The timing generation circuit includes a binary counter constituted of three T-flip-flop circuits, and a binary state at reset of the binary counter is also used at system reset and in generation of the output pulses, to generate eight output pulses having different timings from eight binary states generated by the binary counter and including the state at the reset. At the system reset, a reset signal to the binary counter is delayed, so that an output of a decoder circuit at the reset of the binary counter is delayed. Therefore, the output of the decoder circuit is masked with a fast reset signal, so that the output of the decoder circuit at the system reset can be prevented from being reflected in an output terminal.
1. A timing generation circuit which comprises a binary counter and a decoder circuit, and outputs a pulse signal based on a clock signal and a reset signal,
the timing generation circuit further comprising:
a latch circuit directly connected to a system input terminal and having an output connected to a NOR circuit, and latching the reset signal; and
a delay circuit connected to the system input terminal that delays the reset signal to reset the binary counter, such that the latch circuit is reset prior to the binary counter,
wherein the binary counter consists of three T-flip-flop circuits, and outputs an 8 bit pulse signal, each pulse having a different timing.
2. The timing generation circuit comprising a binary counter and a decoder circuit, and outputting a pulse signal based on a clock signal and a reset signal,
the timing generation circuit further comprising:
a latch circuit that latches the reset signal; and a delay circuit that delays the reset signal to reset the binary counter,
wherein the binary counter includes three T-flip-flop circuits, and outputs an 8 bit pulse signal; and
a D-flip-flop circuit that receives an output signal of the binary counter, and outputs a 9 bit pulse signal.