Active gate drive circuit
View Patent ↗Exemplary embodiments are directed to a gate drive circuit and a method for controlling a gate-controlled component. The gate drive circuit includes a PI controller that receives an input reference signal (v ref,d/dt ) controls a gate voltage of the gate-controlled component. The gate drive circuit also includes a first feedback loop for the PI controller adapted to provide feedback from a time derivative of a collector-to-emitter voltage (v CE ) of the controlled component. The first feedback loop has a first gain (k v ). A second is provided in the gate drive circuit feedback loop for the PI controller that provides feedback from the time derivative of the collector current (i C ) of the controlled component. The second feedback loop has second gain (k i ) and includes a clipping circuit that modifies the feedback signal in the second feedback loop during turn-on of the controlled component when the time derivative of the collector current is negative.
1. A gate drive circuit for controlling a gate-controlled component comprising:
a PI controller configured to receive an input reference signal (v ref,d/dt ) and to control a gate voltage of the gate-controlled component;
a first feedback loop for the PI controller that provides feedback from a time derivative of a collector-to-emitter voltage (v CE ) of the controlled component, the first feedback loop having first gain (k v ); and
a second feedback loop for the PI controller that provides feedback from a time derivative of the collector current (i C ) of the controlled component, the second feedback loop having second gain (k i ),
wherein the second feedback loop includes a clipping circuit that modifies the feedback signal in the second feedback loop during turn-on of the controlled component when the time derivative of the collector current is negative.
2. The gate drive circuit according to claim 1 , comprising:
a gate current control loop connected to the PI controller, wherein the control loop receives a feedback signal from the gate current and is configured to control the gate current during turn-on and turn-off delays.
3. The gate drive circuit according to claim 1 , comprising:
a buffer circuit (BUF) that amplifies an output signal from the PI controller to drive the gate-controlled component.
4. The gate drive circuit according to claim 1 , wherein the clipping circuit comprises a controlled component for enabling the clipping circuit.
5. The gate drive circuit according to claim 4 , wherein the controlled component is a voltage-controlled switch.
6. The gate drive circuit according to claim 4 , wherein once enabled, the clipping circuit limits the output.
7. The gate drive circuit according to claim 1 , wherein the first feedback loop includes a capacitor that is connected to receive a collector-to-emitter voltage of the controlled component, and
wherein the time derivate of the collector-to-emitter voltage is determined as a voltage level due to the capacitor being responsive to the collector-to-emitter voltage change.
8. The gate drive circuit according to claim 1 , wherein the time derivative of the collector current is determined as a voltage level from the voltage over a known inductance of the circuit.
9. The gate drive circuit according to claim 8 , wherein the known inductance of the circuit is a parasitic bonding wire inductance of the emitter.
10. A method for controlling a gate-controlled component by using a PI controller adapted to receive an input reference signal (v ref,d/dt ) and to control a gate voltage of the gate-controlled component, the method comprising:
providing the input reference signal (v ref,d/dt ) to the PI controller;
obtaining, via a first feedback loop, a first feedback signal for the PI controller from a time derivative of a collector-to-emitter voltage (v CE ) of the controlled component;
obtaining, via a second feedback loop, a second feedback signal for the PI controller from the time derivative of the collector current (i C ) of the controlled component; and
modifying the feedback signal in the second feedback loop during turn-on of the controlled component when the time derivative of the collector current is negative.
11. The method according to claim 10 , wherein a capacitor is connected to receive a collector-to-emitter voltage of the gate-controlled component, the method comprising:
determining the time derivate of the collector-to-emitter voltage as a voltage level based on a capacitor that is responsive to a change in the collector-to-emitter voltage.
12. The method according to claim 10 , wherein a gate current control loop is connected to the PI controller, the method comprising:
controlling the gate current during turn-on and turn-off delays based on a feedback signal received by the gate current control loop.
13. The method according to claim 10 , wherein the second feedback loop includes a clipping circuit, the method comprising:
enabling the clipping circuit via a controlled component.
14. The method according to claim 13 , wherein the clipping circuit includes a voltage-controlled switch and enabling the clipping circuit comprises:
applying a voltage to a gate of the voltage-controlled switch.
15. The method according to claim 13 , comprising:
limiting an output of the gate drive circuit when the clipping circuit is enabled.