DE-INTERLEAVING DEVICE, DE-INTERLEAVING METHOD, DATA TRANSMISSION SYSTEM, AND DATA TRANSMISSION METHOD

1 . A de-interleaving device for de-interleaving an input data block interleaved by storing data of an original data block including R×C′ portions of data in a matrix of R columns×C rows in row-major order and reading the data of the original data block in column-major order to restore the original data block, C′ representing any divisor of R×C, the de-interleaving device comprising:

a memory configured to store R×C portions of data;

a write address generator configured to generate, starting from an initial value, a write address of the memory for each input data block based on a first incremental value provided as a difference between the initial value and a c+1th write address for a first-previous input data block stored in the memory, c representing the number of rows when data of the first-previous input data block is stored in the matrix in row-major order;

a read address generator configured to generate, starting from the initial value, a read address of the memory other than a (n×R)+1th read address for each input data block based on the first incremental value, and to generate the (n×R)+1th read address based on a second incremental value provided as a difference between the initial value and a second write address for a first-previous input data block stored in the memory, n being an integer of 0 or more; and

a memory interface configured to successively read data from the read address generated by the read address generator, and to successively write data of the input data block to the write address generated by the write address generator.

2 . The de-interleaving device of claim 1 , wherein

the read address generator includes

a first address generator configured to generate a read address based on a value obtained by adding the first incremental value to a first-previous read address,

a second address generator configured to generate a read address based on a value obtained by adding the second incremental value to a Rth-previous read address,

a multiplexer configured to selectively supply one of the read addresses generated by the first and second address generators to the memory interface, and

a selection controller configured to control selection performed by the multiplexer.

3 . The de-interleaving device of claim 1 , further comprising:

a first register configured to store a first-previous write address;

a second register configured to store a first-previous read address;

an address generator time-shared by the write address generator and the read address generator and configured to generate an address based on a value obtained by adding the first incremental value to a given address;

a multiplexer configured to selectively supply one of addresses stored in the first and second registers to the address generator;

a demultiplexer configured to selectively supply, as one of a read address or a write address, an address generated by the address generator to the memory interface, and

a selection controller configured to control selection performed by the multiplexer and the demultiplexer.

4 . A de-interleaving method for de-interleaving an input data block to restore an original data block by storing, in a memory, the input data block interleaved by storing data of the original data block including R×C′ portions of data in a matrix of R columns×C rows in row-major order and reading the data of the original data block in column-major order, C′ representing any divisor of R×C, the method comprising:

generating a first incremental value provided as a difference between first and c+1th write addresses for a first-previous input data block stored in the memory, c representing the number of rows when data of the first-previous input data block is stored in the matrix in row-major order;

generating a second incremental value provided as a difference between first and second write addresses for a first-previous input data block stored in the memory;

generating, starting from an initial value, a write address of the memory for each input data block based on the first incremental value;

generating, starting from the initial value, a read address of the memory other than a (n×R)+1th read address for each input data block based on the first incremental value, and generating the (n×R)+1th read address based on the second incremental value, n being an integer of 0 or more; and

successively reading data from the generated read address, and successively writing data of an input data block to the generated write address.

5 . A data transmission system comprising:

an interleaving device configured to generate and transmit a data block interleaved by storing data of an original data block including R×C′ portions of data in a matrix of R columns×C rows in row-major order and reading the data of the original data block in column-major order, C′ representing any divisor of R×C; and

the de-interleaving device of claim 1 configured to receive the interleaved data block and to de-interleave the received data block to restore the original data block.

6 . A data transmission method, comprising:

generating and transmitting a data block interleaved by storing data of an original data block including R×C′ portions of data in a matrix of R columns×C rows in row-major order and reading the data of the original data block in column-major order, C′ representing any divisor of R×C; and

receiving the interleaved data block and de-interleaving, according to the method of claim 4 , the received data block to restore the original data block.