Semiconductor device with chip having low-k-layers
View Patent ↗A semiconductor device is described having at least one semiconductor chip, the chip having an active area on a top side thereof, the active area formed at least in part of low-k material, said low-k material defining a low-k subarea of said active area; an embedding material, in which said at least one semiconductor chip is embedded, at least part of the embedding material forming a coplanar area with said active area; at least one contact area within the low-k subarea; a redistribution layer on the coplanar area, the redistribution layer connected to said contact areas; at least one first-level interconnect, located outside said low-k subarea, the first-level interconnect electrically connected to at least one of said contact areas via the redistribution layer.
1. A semiconductor device comprising:
at least one semiconductor chip, the chip comprising: an active area on a top side of the at least one semiconductor chip, the active area being formed at least in part of a low-k material defining a low-k sub-area of the active area;
an embedding material embedding the at least one semiconductor chip, wherein at least part of the embedding material forms a coplanar area with the active area;
at least one contact area disposed within the low-k sub-area; and
at least one interconnect, located outside the low-k sub-area, the interconnect electrically connected to the at least one contact area.
2. The device of claim 1 , further comprising:
a redistribution layer disposed on the coplanar area, wherein the redistribution layer is electrically connected to the at least one contact area.
3. The device of claim 2 , wherein the at least one interconnect is electrically connected to the at least one contact area via the redistribution layer.
4. The device of claim 3 , further comprising:
a dielectric layer disposed on the coplanar area.
5. The device of claim 3 , further comprising:
a protection layer disposed over the low-k sub-area.
6. The device of claim 5 , wherein the protection layer is composed of one or more materials selected from the group consisting of: silicone, polyurethane, epoxy, polyimide.
7. The device of claim 5 , wherein the protection layer comprises silicone particles with one of the following fillers: air gaps, air foams, bubbles.
8. The device of claim 3 , further comprising:
a lid disposed over the active area.
9. The device of claim 8 , wherein the lid is one of a polymer lid, a metal lid and a ceramic lid.
10. The device of claim 8 , wherein the lid is glued, soldered, clamped, or bonded to the active area.
11. The device of claim 1 , wherein the at least one interconnect is located on a back side of the at least one semiconductor chip.
12. The device of claim 11 , wherein the at least one interconnect is electrically connected to the at least one contact area by at least one through-silicon-via.
13. The device of claim 12 , wherein the low-k sub-area is mechanically decoupled from the back side of the at least one chip by at least one layer of silicon.
14. The device of claim 1 , further comprising:
a substrate electrically connected to the at least one interconnect.
15. The device of claim 1 , wherein the at least one interconnect is a flip-chip bump or a copper pillar.
16. A semiconductor device comprising:
at least one semiconductor chip, the chip comprising: an active area on a top side of the at least one semiconductor chip, the active area being formed at least in part of a low-k material defining a low-k sub-area of the active area;
an embedding material embedding the at least one semiconductor chip, wherein at least part of the embedding material forms a coplanar area with the active area;
at least one contact area disposed within the low-k sub-area;
a redistribution layer disposed on the coplanar area, wherein the redistribution layer is electrically connected to the at least one contact area;
at least one interconnect, located outside the low-k subarea, the interconnect electrically connected to the at least one contact area via the redistribution layer.
17. The device of claim 16 , further comprising:
a dielectric layer disposed on the coplanar area.
18. The device of claim 16 , further comprising:
a protection layer applied over the low-k sub-area.
19. The device of claim 18 , wherein the protection layer is composed of one or more materials selected from the group consisting of: silicone, polyurethane, epoxy, polyimide.
20. The device of claim 18 , wherein the protection layer contains silicone particles with one of the following fillers: air gaps, air foams, bubbles.
21. The device of claim 16 , further comprising:
a lid disposed over the active area.
22. The device of claim 21 , wherein the lid is one of a polymer lid, a metal lid and a ceramic lid.
23. The device of claim 21 , wherein the lid is glued, soldered, clamped, or bonded to the active area.
24. The device of claim 16 , further comprising:
a substrate electrically connected to the at least one interconnect.
25. The device of claim 16 , wherein the at least one interconnect is a flip-chip bump or a copper pillar.
26. A method of producing a semiconductor device, comprising:
embedding a semiconductor chip, including a top side with an active area formed at least part of low-k material defining a low-k sub-area, into an embedding material;
forming a planar surface on the embedding material, the active area coplanar with the embedding material;
disposing at least one contact area within the low-k sub-area;
disposing a redistribution layer on the coplanar area, the redistribution layer electrically connected to the at least one contact area;
forming at least one interconnect outside the low-k sub-area, the at least one interconnect electrically connected to the at least one contact area within the low-k sub-area via the redistribution layer.
27. The method of claim 26 , further comprising:
depositing a dielectric layer on the coplanar area.
28. The method of claim 26 , further comprising:
depositing a protection layer over the low-k sub-area.
29. The method of claim 26 , further comprising:
disposing a lid over the low-k sub-area.
30. The method of claim 26 , further comprising:
connecting a substrate electrically with the at least one interconnect.