Granted Patent B2

US 8,813,020 · App. 13/740,195 · Granted Aug 19, 2014

Abstract

Claims (55)

1. A computer-implemented method comprising:

storing a first layout of a circuit on a non-transitory memory medium, wherein the first layout describes a plurality of vertically stacked layers used in a fabrication process to manufacture the circuit, wherein each layer corresponds to a respective step in the fabrication process, wherein the fabrication process would modify geometries of one or more of the layers and result in an electrical connection between a first layer and a second layer of the described plurality of vertically stacked layers, wherein the electrical connection is a design feature of the circuit that is not directly specified by the first layout;

applying, by the computer, a set of rules to the first layout to automatically generate a modified layout for performing an electromagnetic (EM) simulation of the circuit, wherein the modified layout specifies a vertical electrical connection between the first layer and the second layer corresponding to the electrical connection that would result from the fabrication process, wherein the set of rules is particular to the fabrication process; and

storing the modified layout on the non-transitory memory medium, wherein the modified layout enables the electromagnetic (EM) simulation of the circuit to be performed, including EM simulation of the electrical connection using the specified vertical electrical connection.

2. The method of claim 1 ,

wherein said applying the set of rules to the first layout comprises adding a vertical interconnect access (via) to the first layout, wherein the via specifies the vertical electrical connection between the first layer and the second layer.

3. The method of claim 2 ,

wherein said adding the via to the first layout comprises adding a new layer to the plurality of layers, wherein the new layer represents the via.

4. The method of claim 3 , wherein said adding the new layer comprises:

positioning the new layer between the first layer and the second layer; and

configuring the new layer to have a vertical thickness large enough to connect the first layer to the second layer.

5. The method of claim 3 ,

wherein the new layer has a vertical thickness that is proportionally larger than a horizontal width of the new layer.

6. The method of claim 2 , wherein said adding the via to the first layout comprises:

automatically determining a region where the first layer overlaps the second layer; and

adding the via at the region.

7. The method of claim 1 , wherein said applying the set of rules comprises:

automatically creating one or more temporary layers;

creating the vertical electrical connection between the first layer and the second layer using the one or more temporary layers; and

deleting the one or more temporary layers.

8. The method of claim 1 ,

wherein the set of rules is a particular set of rules in a plurality of sets of rules, wherein each of the sets of rules corresponds to a different fabrication process;

wherein the method further comprises:

automatically determining that the first layout is targeted to a particular fabrication process; and

selecting the particular set of rules from the plurality of sets of rules in response to determining that the particular set of rules corresponds to the particular fabrication process.

9. The method of claim 1 , further comprising creating the set of rules, wherein creating the set of rules comprises:

selecting each rule of the set of rules from a library;

configuring one or more of the rules with one or more parameters; and

storing information specifying that the set of rules corresponds to the fabrication process.

10. The method of claim 1 , further comprising:

performing the electromagnetic (EM) simulation of the circuit using the modified layout.

11. A non-transitory memory medium storing program instructions executable by one or more processors to:

receive a first layout of a circuit, wherein the first layout describes a plurality of vertically stacked layers used in a fabrication process to manufacture the circuit, wherein each layer corresponds to a respective step in the fabrication process, wherein the fabrication process would modify geometries of one or more of the layers and result in an electrical connection between a first layer and a second layer of the described plurality of vertically stacked layers, wherein the electrical connection is a design feature of the circuit that is not directly specified by the first layout;

apply a set of rules to the first layout to automatically generate a modified layout for performing an electromagnetic (EM) simulation of the circuit, wherein the modified layout specifies a vertical electrical connection between the first layer and the second layer corresponding to the electrical connection that would result from the fabrication process, wherein the set of rules is particular to the fabrication process; and

store the modified layout, wherein the modified layout enables the electromagnetic (EM) simulation of the circuit to be performed, including EM simulation of the electrical connection using the specified vertical electrical connection.

12. The non-transitory memory medium of claim 11 ,

wherein said applying the set of rules to the first layout comprises adding a vertical interconnect access (via) to the first layout, wherein the via specifies the vertical electrical connection between the first layer and the second layer.

13. The non-transitory memory medium of claim 12 ,

wherein said adding the via to the first layout comprises adding a new layer to the plurality of layers, wherein the new layer represents the via.

14. The non-transitory memory medium of claim 13 , wherein said adding the new layer comprises:

positioning the new layer between the first layer and the second layer; and

configuring the new layer to have a vertical thickness large enough to connect the first layer to the second layer.

15. A system comprising:

one or more processors; and

memory storing program instructions, wherein the program instructions are executable by one or more processors to:

receive a first layout of a circuit, wherein the first layout describes a plurality of vertically stacked layers used in a fabrication process to manufacture the circuit, wherein each layer corresponds to a respective step in the fabrication process, wherein the fabrication process would modify geometries of one or more of the layers and result in an electrical connection between a first layer and a second layer of the described plurality of vertically stacked layers, wherein the electrical connection is a design feature of the circuit that is not directly specified by the first layout;

apply a set of rules to the first layout to automatically generate a modified layout for performing an electromagnetic (EM) simulation of the circuit, wherein the modified layout specifies a vertical electrical connection between the first layer and the second layer corresponding to the electrical connection that would result from the fabrication process, wherein the set of rules is particular to the fabrication process; and

store the modified layout, wherein the modified layout enables the electromagnetic (EM) simulation of the circuit to be performed, including EM simulation of the electrical connection using the specified vertical electrical connection.

16. The system of claim 15 ,

wherein said applying the set of rules to the first layout comprises adding a vertical interconnect access (via) to the first layout, wherein the via specifies the vertical electrical connection between the first layer and the second layer.

17. The system of claim 16 ,

wherein said adding the via to the first layout comprises adding a new layer to the plurality of layers, wherein the new layer represents the via.

18. The system of claim 17 , wherein said adding the new layer comprises:

positioning the new layer between the first layer and the second layer; and

configuring the new layer to have a vertical thickness large enough to connect the first layer to the second layer.

Assignments (6)