Apparatus and method to manage energy capacity of a backup power supply

1. A process of managing a backup capacitor power source, the method comprising:

checking if a non-volatile memory comprises un-erased areas;

only if the non-volatile memory comprises un-erased areas, elevating a backup capacitor potential to and then beyond a first predetermined operating potential sufficient to power a backup of a volatile memory to the non-volatile memory, to a second predetermined operating potential exceeding the first predetermined operating potential;

ERASING the un-erased areas; and

returning the capacitor to the predetermined operating potential after the ERASE is complete.

2. The process of claim 1 , further comprising:

ERASING the un-erased areas, prior to returning the capacitor to the predetermined operating potential, using a primary power source for the volatile and non-volatile memories.

3. The process of claim 1 , further comprising:

ERASING the un-erased areas using the backup capacitor as a power source for the volatile and non-volatile memories while a primary power source for the volatile and non-volatile memories is available.

4. The process of claim 1 , further comprising:

inhibiting writing of data to the volatile memory until the capacitor reaches the elevated potential (a) while primary power is available and (b) after the capacitor reaches a sufficient charge to complete a full backup of the volatile memory to the nonvolatile memory.

5. The process of claim 1 , wherein checking if the non-volatile memory comprises un-erased areas comprises checking if the non-volatile memory comprises data to restore to the volatile memory.

6. The process of claim 3 , wherein returning the capacitor to the predetermined operating potential after the ERASE is complete further comprises powering the ERASE using the backup capacitor as a power source for the ERASE.

7. A memory device comprising:

volatile memory;

non-volatile memory; and

logic to check if the non-volatile memory comprises un-erased areas, and only if the non-volatile memory comprises un-erased areas, elevating a backup capacitor potential to and then beyond a first predetermined operating potential sufficient to power a backup of a volatile memory to the non-volatile memory, to a second predetermined operating potential exceeding the first predetermined operating potential;

logic to ERASE the un-erased areas; and

logic to return the capacitor to the predetermined operating potential after the ERASE is complete.

8. The memory device of claim 7 , further comprising:

logic to ERASE the un-erased areas, prior to returning the capacitor to the predetermined operating potential, using a primary power source for the volatile and non-volatile memories.

9. The memory device of claim 7 , further comprising:

logic to ERASE the un-erased areas using the backup capacitor as a power source for the volatile and non-volatile memories while a primary power source for the volatile and non-volatile memories is available.

10. The memory device of claim 7 , further comprising:

logic to inhibit writing of data to the volatile memory until the capacitor reaches the elevated potential (a) while primary power is available to the volatile and nonvolatile memories and (b) after the capacitor reaches a sufficient charge to complete a full backup of the volatile memory to the nonvolatile memory.

11. The memory device of claim 7 , wherein the logic to check if the non-volatile memory comprises un-erased areas comprises logic to check if the non-volatile memory comprises data to restore to the volatile memory.

12. The memory device of claim 11 , wherein the logic to return the capacitor to the predetermined operating potential after the ERASE is complete further comprises logic to power the ERASE using the backup capacitor as a power source for the ERASE.

13. A controller device for a memory system, comprising:

logic to check if a non-volatile memory comprises un-erased areas, and only if the non-volatile memory comprises un-erased areas, elevating a backup capacitor potential to and then beyond a first predetermined operating potential sufficient to power a backup of a volatile memory to the non-volatile memory, to a second predetermined operating potential exceeding the first predetermined operating potential;

logic to ERASE the un-erased areas; and

logic to return the capacitor to the predetermined operating potential after the ERASE is complete.

14. The controller device of claim 13 , further comprising:

logic to ERASE the un-erased areas, prior to returning the capacitor to the predetermined operating potential, using a primary power source for the volatile and non-volatile memories.

15. The controller device of claim 13 , further comprising:

logic to ERASE the un-erased areas using the backup capacitor as a power source for the volatile and non-volatile memories while a primary power source for the volatile and non-volatile memories is available.

16. The controller device of claim 13 , further comprising:

logic to inhibit writing of data to the volatile memory until the capacitor reaches the elevated potential (a) while primary power is available to the volatile and nonvolatile memories and (b) after the capacitor reaches a sufficient charge to complete a full backup of the volatile memory to the nonvolatile memory.

17. The controller device of claim 13 , wherein the logic to check if the non-volatile memory comprises un-erased areas comprises logic to check if the non-volatile memory comprises data to restore to the volatile memory.

18. The controller device of claim 15 , wherein the logic to return the capacitor to the predetermined operating potential after the ERASE is complete further comprises logic to power the ERASE using the backup capacitor as a power source for the ERASE.