Compound semiconductor device and manufacturing method of the same
An electrode ( 109 ) insulated from a compound semiconductor layer ( 102 ) and being in contact with an electrode ( 101 ) and a compound semiconductor layer ( 103 ) is provided. A lattice constant of the compound semiconductor layer ( 103 ) is smaller than both of a lattice constant of the compound semiconductor layer ( 102 ) and a lattice constant of a compound semiconductor layer ( 104 ), and a lattice constant of a compound semiconductor layer ( 107 ) is smaller than both of the lattice constants of the compound semiconductor layer ( 102 ) and the lattice constants of the compound semiconductor layer ( 104 ). A conduction band energy of the compound semiconductor layer ( 103 ) is higher than a conduction band energy of the compound semiconductor layer ( 104 ).
1. A compound semiconductor device, comprising:
a substrate whose upper surface is a non-polarity surface;
a first electrode formed over the substrate;
a first compound semiconductor layer formed over the first electrode;
a second compound semiconductor layer formed on the first compound semiconductor layer;
a third compound semiconductor layer formed on the second compound semiconductor layer;
a second electrode formed over the third compound semiconductor layer;
a fourth compound semiconductor layer formed in an opening formed in a stack of the first compound semiconductor layer, the second compound semiconductor layer and the third compound semiconductor layer, the fourth compound semiconductor layer being in contact with side surfaces of the first compound semiconductor layer, the second compound semiconductor layer and the third compound semiconductor layer, and the side surfaces facing to the opening;
a gate electrode that controls an electric potential of an interface between the second compound semiconductor layer and the fourth compound semiconductor layer; and
a third electrode insulated from the first compound semiconductor layer, the third electrode being in contact with the first electrode and the second compound semiconductor layer, wherein
a lattice constant of the second compound semiconductor layer is smaller than both of a lattice constant of the first compound semiconductor layer and a lattice constant of the third compound semiconductor layer,
a lattice constant of the fourth compound semiconductor layer is smaller than both of the lattice constant of the first compound semiconductor layer and the lattice constant of the third compound semiconductor layer, and
a conduction band energy of the second compound semiconductor layer is higher than a conduction band energy of the third compound semiconductor layer.
2. The compound semiconductor device according to claim 1 , wherein the third electrode is formed apart from two-dimensional electron gas generated resulting from a difference of the lattice constants between the first compound semiconductor layer and the fourth compound semiconductor layer and two-dimensional electron gas generated resulting from a difference of the lattice constants between the third compound semiconductor layer and the fourth compound semiconductor layer.
3. The compound semiconductor device according to claim 1 , wherein the lattice constant of the second compound semiconductor layer is equal to or less than the lattice constant of the fourth compound semiconductor layer.
4. The compound semiconductor device according to claim 1 , further comprising a gate insulating film that insulates the gate electrode and the fourth compound semiconductor layer from each other.
5. The compound semiconductor device according to claim 4 , further comprising an insulating film thicker than the gate insulating film, the insulating film insulating the gate electrode and the first electrode from each other.
6. The compound semiconductor device according to claim 1 , wherein the first electrode and the third electrode are integrally formed.
7. The compound semiconductor device according to claim 1 , wherein
each of the first compound semiconductor layer, the second compound semiconductor layer and the third compound semiconductor layer contains Ga and N, and
each of front surfaces of the first compound semiconductor layer, the second compound semiconductor layer and the third compound semiconductor layer is perpendicular to an a-axis direction.
8. The compound semiconductor device according to claim 1 , wherein
each of the first compound semiconductor layer, the second compound semiconductor layer and the third compound semiconductor layer contains Ga and N, and
a plane orientation of each of the side surfaces is (0001).
9. The compound semiconductor device according to claim 1 , wherein a resistance of the third compound semiconductor layer at the second electrode side is lower than a resistance of the third compound semiconductor layer at the second compound semiconductor layer side.
10. The compound semiconductor device according to claim 1 , wherein
each of the first compound semiconductor layer and the third compound semiconductor layer is a GaN layer or an AlGaN layer, and
each of the second compound semiconductor layer and the fourth compound semiconductor layer is an AlGaN layer containing Al at higher ratio than both of the first compound semiconductor layer and the third compound semiconductor layer.
11. The compound semiconductor device according to claim 4 , wherein the gate insulating film comprises at least one kind selected from the group consisting of a silicon nitride film, a hafnium oxide film, a tantalum oxide film and an aluminum oxide film.
12. The compound semiconductor device according to claim 5 , wherein the insulating film comprises at least one kind selected from the group consisting of a silicon nitride film, a hafnium oxide film, a tantalum oxide film and an aluminum oxide film.