Systems and methods for reducing frequency pulling in an oscillator circuit
View Patent ↗Methods and systems are provided to calibrate an oscillator circuit to reduce frequency pulling as a result of a change in power to a portion of the oscillator circuit. In an embodiment, an oscillator is coupled to a clock buffer circuit and a tuning capacitor configured to tune a frequency of the oscillator to a baseline frequency required for cellular communications. A change in power to the clock buffer circuit initiates a change in an amount of capacitance seen by the oscillator, which negatively impacts the tuning of the oscillator. A register stores a frequency offset caused by the change in power, and the tuning capacitor is adjusted, using the frequency offset, in response to the change in power, such that the total amount of capacitance seen by the oscillator is not changed when the change in power occurs.
1. An oscillator circuit, comprising:
a first clock buffer circuit coupled to an oscillator;
a second clock buffer circuit coupled to the oscillator;
a tuning capacitor coupled to the oscillator; and
a controller configured to:
detect a first change in power to the first clock buffer circuit,
detect a second change in power to the second clock buffer circuit, and
adjust, in response to detecting the respective first and second changes in power, the tuning capacitor to tune a frequency of the oscillator to a desired baseline frequency.
2. The oscillator circuit of claim 1 , wherein the first change in power causes a first frequency offset in the frequency of the oscillator, and wherein the second change in power causes a second frequency offset in the frequency of the oscillator.
3. The oscillator circuit of claim 2 , wherein the controller is further configured to:
adjust the tuning capacitor based on the respective first and second frequency offsets.
4. The oscillator circuit of claim 1 , wherein the oscillator is a digitally compensated crystal oscillator (DCXO) core.
5. The oscillator circuit of claim 1 , wherein the first clock buffer circuit is changed from an off-state to an on-state to initiate the first change in power.
6. The oscillator circuit of claim 1 , wherein the first clock buffer circuit is changed from an off-state to a standby state or from the standby state to an on-state to initiate the first change in power.
7. The oscillator circuit of claim 1 , wherein the controller is further configured to adjust the tuning capacitor using a temperature value caused by the first change in power.
8. A method comprising:
detecting a first change in power to a first clock buffer circuit of an oscillator circuit;
detecting a second change in power to a second clock buffer circuit of the oscillator circuit; and
adjusting, in response to detecting the respective first and second changes in power, a tuning capacitor to tune a frequency of an oscillator to a desired baseline frequency.
9. The method of claim 8 , wherein the first change in power causes a first frequency offset in the frequency of the oscillator, and wherein the second change in power causes a second frequency offset in the frequency of the oscillator.
10. The method of claim 9 , further comprising:
adjusting the tuning capacitor based on the respective first and second frequency offsets.
11. The method of claim 8 , wherein the oscillator is a digitally compensated crystal oscillator (DCXO) core.
12. The method of claim 8 , wherein the first clock buffer circuit is changed from an off-state to an on-state to initiate the first change in power.
13. The method of claim 8 , wherein the first clock buffer circuit is changed from an off-state to a standby state or from the standby state to an on-state to initiate the first change in power.
14. The method of claim 8 , further comprising adjusting the tuning capacitor using a temperature value caused by the first change in power.
15. An oscillator circuit comprising:
a first clock buffer circuit coupled to an oscillator;
a second clock buffer circuit coupled to the oscillator; and
a tuning capacitor coupled to the oscillator, wherein the tuning capacitor is configured to adjust, in response to detecting a first change in power to the first clock buffer circuit and a second change in power to the second clock buffer circuit, a frequency of the oscillator to a desired baseline frequency.
16. The oscillator circuit of claim 15 , wherein the first change in power causes a first frequency offset in the frequency of the oscillator, and wherein the second change in power causes a second frequency offset in the frequency of the oscillator.
17. The oscillator circuit of claim 16 , wherein the tuning capacitor is further configured to:
adjust the frequency of the oscillator based on the respective first and second frequency offsets.
18. The oscillator circuit of claim 15 , wherein the oscillator is a digitally compensated crystal oscillator (DCXO) core.
19. The oscillator circuit of claim 15 , wherein the first clock buffer circuit is changed from an off-state to an on-state, from the off-state to a standby state, or from the standby state to the on-state to initiate the first change in power.
20. The oscillator circuit of claim 15 , wherein the tuning capacitor is further configured to adjust the frequency of the oscillator using a temperature value caused by the first change in power.