Memory controller and memory access system with error detection using data comparison of loop-backed signals
View Patent ↗A controller section outputs a first signal and a second signal holding a phase relationship with the first signal. The second signal is received by a memory I/F section via a FIFO memory of an error detecting section. The memory I/F section performs timing adjustment for the first and second signals, outputs the first and second signals after the timing adjustment to a memory, and loops back the second signal. A data comparator compares the looped-back second signal with the original second signal outputted from the FIFO memory and corresponding to the looped-back signal.
1. A memory controller which performs data input/output with a memory, comprising:
a controller section configured to transmit/receive data to/from circuit blocks and generate and output a first signal and a second signal holding a predetermined phase relationship with the first signal;
an error detecting section having a FIFO memory configured to receive as an input the second signal outputted from the controller section; and
a memory I/F section configured to receive as inputs the first signal outputted from the controller section and the second signal outputted from the FIFO memory of the error detecting section, perform timing adjustment for the first and second signals, and output the first and second signals after the timing adjustment to the memory,
wherein the second signal outputted from the memory I/F section is outputted to the memory and is looped back to the error detecting section, and
the error detecting section includes:
a data comparator configured to compare the looped-back second signal with the original second signal outputted from the FIFO memory and corresponding to the looped-back second signal; and
a register configured to store a comparison result of the data comparator, and
wherein the controller section outputs a block identifying signal indicating one of the circuit blocks which is an output source of the second signal to the error detecting section, and
when the comparison result of the data comparator is mismatch, the error detecting section stores the block identifying signal with the comparison result in the register.
2. The memory controller of claim 1 , wherein the first signal is a clock signal and the second signal is a command signal.
3. The memory controller of claim 1 , wherein the first signal is a data strobe signal and the second signal is a data signal.
4. A memory access system, comprising:
the memory controller of claim 1 ; and
an output terminal configured to externally monitor stored data of the register of the memory controller.
5. A memory access system, comprising:
the memory controller of claim 1 ; and
a CPU configured to monitor stored data of the register of the memory controller.
6. The memory access system of claim 5 , further comprising:
a power supply control section configured to control a power supply voltage to be given to the memory controller by control of the CPU.