IP Library Granted Patent US 9,099,041
Granted Patent B2
US 9,099,041 · App. 13/743,629 · Granted Aug 4, 2015

Display device with a correction period of a threshold voltage of a driver transistor and electronic apparatus

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 9,099,041
App. No.
13/743,629
Granted
Aug 4, 2015
Kind
B2
Abstract

A display device includes pixel array unit and a driver unit. A sampling transistor samples a signal potential to hold the signal potential in a holding capacitor. A driver transistor flows a drive current to a light emitting element in accordance with the signal potential held. A main scanner in the driver unit outputs the control signal having a shorter pulse width than the time period to the scan line to make the sampling transistor conductive during a time period while the signal line is at the signal potential, thereby adding the signal potential a correction for a mobility of the driver transistor when the signal potential is held in the holding capacitor.

Claims (44)

1. A display device comprising:

a pixel array unit including scan lines, signal lines, pixels configured to form a matrix, and power supply lines,

at least one of the pixels including

a light emitting element,

a sampling transistor configured to be conductive during a sampling period in response to a control signal and configured to sample a signal potential from said signal line,

a holding capacitor configured to receive a sampled signal potential,

a driver transistor configured to receive a supply of a current from one of the power supply lines at a first potential and to send a drive current to the light emitting element in accordance with the sampled signal potential, and

wherein the sampling period is shorter than a time period during which the signal line is at the signal potential,

wherein the sampling period and a correction period of the sampled signal potential are performed at the same time, and

wherein the driver transistor is configured to send a correction current to the holding capacitor in the correction period to decrease a potential difference between two terminals of the holding capacitor.

2. The display device according to claim 1 , wherein the sampling period starts after a start of the time period during which the signal line is at the signal potential and the sampling period ends before an end of the time period during which the signal line is at the signal potential.

3. The display device according to claim 2 , wherein the driver transistor is configured to send the correction current to start the correction period of the sampled signal potential.

4. The display device according to claim 3 , wherein the higher the sampled signal potential is the larger the correction current becomes.

5. The display device according to claim 3 , wherein the higher the sampled signal potential is the larger a correction potential becomes.

6. The display device according to claim 3 , wherein during the sampling period, a luminance difference due to a delay of a waveform of the signal line can be suppressed.

7. The display device according to claim 1 , further comprising a capacitor disposed between a control terminal of the driver transistor and a control terminal of the sampling transistor.

8. An electronic device comprising the display device according to claim 1 .

9. A display device comprising:

a pixel array unit including scan lines, signal lines, pixels configured to form a matrix, and power supply lines,

at least one of the pixels including

a light emitting element,

a holding capacitor,

a driver transistor, and

a sampling transistor configured to be conductive during a sampling period in response to a control signal and configured to charge a signal potential in the holding capacitor, and

wherein the sampling period is shorter than a time period during which the signal line is at the signal potential,

wherein the sampling period and a correction period of the sampled signal potential are performed at the same time; and

wherein the driver transistor is configured to send a correction current to the holding capacitor in the correction period to decrease a potential difference between two terminals of the holding capacitor.

10. The display device according to claim 9 , wherein the sampling period starts after a start of the time period during which the signal line is at the signal potential and the sampling period ends before an end of the time period during which the signal line is at the signal potential.

11. The display device according to claim 10 , wherein the driver transistor is configured to send the correction current to start the correction period of the sampled signal potential.

12. The display device according to claim 11 , wherein the higher the sampled signal potential is the larger the correction current becomes.

13. The display device according to claim 11 , wherein the higher the sampled signal potential is the larger a correction potential becomes.

14. The display device according to claim 11 , wherein during the sampling period, a luminance difference due to a delay of a waveform of the signal line can be suppressed.

15. The display device according to claim 9 , further comprising a capacitor disposed between a control terminal of the driver transistor and a control terminal of the sampling transistor.

16. An electronic device comprising the display device according to claim 9 .

17. A display device comprising:

a pixel array unit including scan lines, signal lines, pixels forming a matrix, and power supply lines,

at least one of the pixels including a light emitting element, a sampling transistor, a driver transistor, and a holding capacitor,

wherein the sampling transistor is configured to become conductive in response to a control signal, and configured to sample a signal potential from one of the column signal lines to hold a sampled signal potential in the holding capacitor,

wherein the driver transistor is configured to receive a supply of a current from one of the power supply lines at a first potential and configured to supply a drive current to the light emitting element in accordance with the sampled signal potential,

the control signal has a pulse width that is shorter than a time period during which one of the column signal lines is at the signal potential such that the sampling transistor is conductive during the time period, and such that the sampling transistor becomes conductive after a start of the time period, and

wherein a correction period of the sampled signal potential is performed during the time period; and

wherein the driver transistor is configured to send a correction current to the holding capacitor in the correction period to decrease a potential difference between two terminals of the holding capacitor.

18. The display device according to claim 17 , further comprising a capacitor disposed between a control terminal of the driver transistor and a control terminal of the sampling transistor.

19. An electronic device comprising the display device according to claim 17 .

Assignments (5)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 18, 2025
From: JDI DESIGN AND DEVELOPMENT G.K.
To: MAGNOLIA BLUE CORPORATION
Reel/Frame 072039/0656 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 31, 2024
From: JOLED, INC.
To: JDI DESIGN AND DEVELOPMENT G.K.
Reel/Frame 066382/0619 →
CORRECTION BY AFFIDAVIT FILED AGAINST REEL/FRAME 063396/0671 Recorded Jun 12, 2023
From: JOLED, INC.
To: JOLED, INC.
Reel/Frame 064067/0723 →
SECURITY INTEREST Recorded Apr 20, 2023
From: JOLED, INC.
To: INCJ, LTD.
Reel/Frame 063396/0671 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 10, 2015
From: SONY CORPORATION
To: JOLED INC.
Reel/Frame 036090/0968 →