Read voltage generation circuit, memory and memory system including the same
View Patent ↗A read voltage generation circuit includes a register unit configured to store an initial read voltage code, a counter circuit configured to change a read voltage code in every read-retry operation, wherein an initial value of the read voltage code is the initial read voltage code; and a voltage generation circuit configured to generate a read voltage corresponding to a read voltage code produced by the counter circuit.
1. A read voltage generation circuit comprising:
a register unit configured to store an initial read voltage code;
a counter circuit configured to change a read voltage code in every read-retry operation, wherein an initial value of the read voltage code is the initial read voltage code; and
a voltage generation circuit configured to generate a read voltage corresponding to the read voltage code produced by the counter circuit,
wherein a counting step of the counter circuit is set to be small when a memory block that is provided with the read voltage operates as a Multi-Level Cell (MLC), and is set to be large when the memory block that is provided with the read voltage operates as a Single-Level Cell (SLC).
2. A read voltage generation circuit comprising:
a register unit configured to store an initial read voltage code;
a counter circuit configured to change a read voltage code in every read-retry operation, wherein an initial value of the read voltage code is the initial read voltage code; and
a voltage generation circuit configured to generate a read voltage corresponding to the read voltage code produced by the counter circuit,
wherein a counting step of the counter circuit is set to be small, when an erase/write cycle of a memory block that is provided with the read voltage becomes high.
3. A memory comprising:
a plurality of memory blocks;
a row circuit configured to apply a read voltage to a selected page in a selected memory of the plurality of memory blocks;
a data access circuit configured to read data from the selected page;
a register configured to store an initial read voltage code;
a counter circuit configured to change a read voltage code in every read-retry operation, wherein an initial value of the read voltage code is the initial read voltage code; and
a voltage generation circuit configured to generate the read voltage corresponding to the read voltage code produced by the counter circuit,
wherein a counting step of the counter circuit is set to be small when the selected memory operates as an MLC, and is set to be large when the selected memory operates as an SLC.
4. A memory comprising:
a plurality of memory blocks;
a row circuit configured to apply a read voltage to a selected page in a selected memory of the plurality of memory blocks;
a data access circuit configured to read data from the selected page;
a register configured to store an initial read voltage code;
a counter circuit configured to change a read voltage code in every read-retry operation, wherein an initial value of the read voltage code is the initial read voltage code; and
a voltage generation circuit configured to generate the read voltage corresponding to the read voltage code produced by the counter circuit,
wherein a counting step of the counter circuit is set to be small, when an erase/write cycle of the selected memory becomes high.
5. A memory system comprising:
a memory configured to include a plurality of memory blocks and a read voltage generation circuit configured to generate a read voltage that is the reference of reading of a selected memory in the memory blocks; and
a memory controller configured to give an instruction of a read-retry operation on the selected memory block to the memory, when reading on the selected memory block has failed,
wherein the read voltage generation circuit includes:
a register configured to store an initial read voltage code;
a counter circuit configured to change a read voltage code in every read-retry operation, wherein an initial value of the read voltage code is the initial read voltage code; and
a voltage generation circuit configured to generate a read voltage corresponding to the read voltage code produced by the counter circuit,
wherein a counting step of the counter circuit is set to be small when the selected memory operates as an MLC, and is set to be large when the selected memory operates as an SLC.
6. A memory system comprising:
a memory configured to include a plurality of memory blocks and a read voltage generation circuit configured to generate a read voltage that is the reference of reading of a selected memory in the memory blocks; and
a memory controller configured to give an instruction of a read-retry operation on the selected memory block to the memory, when reading on the selected memory block has failed,
wherein the read voltage generation circuit includes:
a register configured to store an initial read voltage code:
a counter circuit configured to change a read voltage code in every read-retry operation, wherein an initial value of the read voltage code is the initial read voltage code; and
a voltage generation circuit configured to generate a read voltage corresponding to the read voltage code produced by the counter circuit,
wherein a counting step of the counter circuit is set to be small when an erase/write cycle of the selected memory is increased.