IP Library Granted Patent US 9,059,137
Granted Patent B2
US 9,059,137 · App. 13/745,291 · Granted Jun 16, 2015

Semiconductor device and method of manufacturing semiconductor device

Inventors: Yoshihiro Hayashi (Kawasaki, JP); Naoya Inoue (Kawasaki, JP); Kishou Kaneko (Kawasaki, JP)
Assignee: Renesas Electronics Corporation
H01L29/41H01L21/28282H01L27/1225H01L29/42344H01L29/42352H01L29/792H01L27/124H01L29/242
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Quick Facts
Patent No.
US 9,059,137
App. No.
13/745,291
Granted
Jun 16, 2015
Kind
B2
Abstract

A semiconductor device, includes a semiconductor substrate, a first interconnect layer formed over the semiconductor substrate, a gate electrode formed in the first interconnect layer, a gate insulating film formed over the gate electrode, a second interconnect layer formed over the gate insulating film, an oxide semiconductor layer formed in the second interconnect layer, and a via formed in the second interconnect layer and connected to the oxide semiconductor layer. The gate electrode, the gate insulating film and the oxide semiconductor layer overlap in a plan view.

Claims (21)

1. A semiconductor device, comprising:

a semiconductor substrate;

a first interconnect layer formed over the semiconductor substrate;

a gate electrode formed in the first interconnect layer;

a gate insulating film formed over the gate electrode;

a second interconnect layer formed over the gate insulating film;

an oxide semiconductor layer formed in the second interconnect layer; and

a via formed in the second interconnect layer and connected to the oxide semiconductor layer;

wherein the gate electrode, the gate insulating film and the oxide semiconductor layer overlap in a plan view;

wherein said oxide semiconductor layer includes a channel region formed in said oxide semiconductor layer;

wherein a trapping film is positioned over said oxide semiconductor layer; and

wherein a back-gate electrode is positioned over said trapping film, and overlaps with said channel region in a plan view.

2. The semiconductor device as claimed in claim 1 , wherein

said first interconnect comprises a copper interconnect,

said gate insulating film functions as a diffusion blocking film, and

said oxide semiconductor layer is formed over said diffusion blocking film.

3. The semiconductor device as claimed in claim 1 ,

wherein said oxide semiconductor layer, said gate insulating film, said gate electrode, said trapping film, and said back-gate electrode configure a memory element.

4. The semiconductor device as claimed in claim 1 , wherein said oxide semiconductor layer comprises at least one of an InGaZnO layer and a ZnO layer.

5. The semiconductor device as claimed in claim 1 , further comprising a MOS (metal-oxide-semiconductor) transistor-type element formed over said semiconductor substrate.

6. The semiconductor device as claimed in claim 5 , wherein at least a part of said MOS transistor-type element overlaps with said oxide semiconductor layer in a plan view.

Assignments (1)
CHANGE OF ADDRESS Recorded Nov 29, 2017
From: RENESAS ELECTRONICS CORPORATION
To: RENESAS ELECTRONICS CORPORATION
Reel/Frame 044928/0001 →
Priority Claims (1)
JP 2008-318098 · Dec 15, 2008 · national
Continuity (2)
Continuation 12654205 · Dec 14, 2009
Related Publication 20130134418A1 · May 30, 2013