Multi-pass system and method supporting multiple streams of video
View Patent ↗Systems and methods are disclosed for performing multiple processing of data in a network. In one embodiment, the network comprises a first display pipeline that is formed in real time from a plurality of possible display pipelines and that performs at least a first processing step on received data. A buffer stores the processed data and a second display pipeline that is formed in real time from a plurality of possible display pipelines performs at least a second processing step on stored data.
1. A method for data processing, the method comprising:
routing, in real time, a data stream to a first plurality of processing nodes to generate a first data stream;
fetching, by a DMA controller, an instruction from a register update list;
sending the instruction to a routing node to control routing of the first data stream amongst a plurality of processing nodes, wherein a processing node is controlled according to the instruction and the plurality of processing nodes comprises the first plurality of processing nodes; and
routing, in real time, the first data stream to a second plurality of processing nodes to generate a second data stream, wherein the plurality of processing nodes comprises the second plurality of processing nodes.
2. The method of claim 1 , wherein the data stream is a video input.
3. The method of claim 1 , wherein the data stream is stored in memory.
4. The method of claim 1 , wherein the DMA controller provides memory access to the processing node.
5. The method of claim 1 , wherein the second data stream is a video output.
6. The method of claim 1 , wherein routing the data stream creates a processing pipeline between at least two processing nodes.
7. A system for data processing, the system comprising:
a first plurality of processing nodes operable to receive a data stream and generate a first data stream, wherein a plurality of processing nodes comprises the first plurality of processing nodes;
a DMA controller operable to fetch an instruction from a register update list and provide the instruction to a routing node to control routing of the first data stream amongst the plurality of processing nodes; and
a routing node operable to receive the instruction from the DMA controller and based on the instruction, route, in real time, the first data stream to a second plurality of processing nodes to generate a second data stream, wherein the plurality of processing nodes comprises the second plurality of processing nodes.
8. The system of claim 7 , wherein the data stream is a video input.
9. The system of claim 7 , further comprising memory to store the data stream.
10. The system of claim 7 , wherein the DMA controller is operable to provide memory access to the processing node.
11. The system of claim 7 , wherein the second data stream is a video output.
12. The system of claim 7 , wherein the DMA controller is operable to adaptively control the routing node.
13. The system of claim 7 , wherein the routing node creates a processing pipeline between at least two processing nodes.
14. The system of claim 7 , further comprising a capture module configured to capture an output of the first plurality of processing nodes and store the output in a frame buffer.
15. A multi-media display device comprising:
a first plurality of processing nodes operable to receive a video input and generate a first data stream;
a routing node operable to route, in real time, the first data stream to a second plurality of processing nodes, wherein the routing node creates a processing pipeline between at least one processing node in the first plurality of processing nodes and at least one processing node in the second plurality of processing nodes;
a DMA controller operable to provide memory access to the first plurality of processing nodes and control the routing node, wherein the DMA controller is operable to fetch an instruction from a register update list and provide the instruction to the routing node to configure the processing pipeline.
16. The display device of claim 15 , wherein the video input is stored in memory.
17. The display device of claim 15 , wherein the DMA controller is operable to provide memory access to the at least one processing node.
18. The display device of claim 15 , wherein the second plurality of processing nodes generate a video output.
19. The display device of claim 15 , further comprising a control register to configure the at least one processing node.
20. The display device of claim 15 , further comprising a capture module configured to capture an output of the first plurality of processing nodes and store the output in a frame buffer.