Stopping criteria for layered iterative error correction

1. A method, comprising:

receiving a codeword with an error correction circuit;

iteratively error correcting the codeword with the error correction circuit including:

parity checking the codeword on a layer-by-layer basis, wherein a layer comprises a fraction of an iteration; and

updating the codeword after each layer; and

stopping the iterative error correction in response to a parity check being correct for a particular layer of a particular iteration without error correcting a next layer of the particular iteration, wherein the particular layer is a fraction other than a last fraction of the particular iteration, and wherein the parity check being correct for the particular layer comprises the parity check resulting in less than a threshold number of parity errors.

2. The method of claim 1 , wherein stopping the iterative error correction comprises stopping the iterative error correction in response to the parity check being correct for the particular layer within a threshold number of units of data.

3. The method of claim 1 , wherein stopping the iterative error correction comprises stopping the iterative error correction in response to the parity check being correct for the particular layer for all units of data.

4. The method of claim 1 , wherein the method includes transferring the codeword to a different error correction circuit after stopping the iterative error correction.

5. The method of claim 4 , wherein iteratively error correcting the codeword with the error correction circuit comprises using a quasi-cyclic low density parity check code to error correct the codeword; and

wherein the method includes using an algebraic code to error correct the codeword with the different error correction circuit.

6. The method of claim 1 , wherein stopping the iterative error correction comprises stopping the iterative error correction in response to the parity check being correct for the particular layer and at least one other layer.

7. The method of claim 6 , wherein stopping the iterative error correction comprises stopping the iterative error correction in response to the parity check being correct for the particular layer and the at least one other layer within a threshold number of units of data.

8. The method of claim 6 , wherein stopping the iterative error correction comprises stopping the iterative error correction in response to the parity check being correct for the particular layer and the at least one other layer for all units of data.

9. A method, comprising:

receiving a codeword with a first error correction circuit;

iteratively error correcting the codeword on a layer-by-layer basis with the first error correction circuit, wherein a layer comprises a fraction of an iteration;

updating the codeword after each layer with the first error correction circuit; and

transferring the codeword to a second error correction circuit in response to a parity check being correct for a particular layer, wherein the particular layer is a fraction other than a last fraction of a particular iteration, and wherein the parity check being correct for the particular layer comprises the parity check resulting in less than a threshold number of parity errors.

10. The method of claim 9 , wherein the method includes transferring the codeword to the second error correction circuit in response to a threshold number of iterations being completed regardless of whether a parity check is correct for a last layer of a last iteration.

11. The method of claim 10 , wherein transferring the codeword comprises transferring a copy of the codeword; and

wherein the method includes continuing iteratively error correcting the codeword with the first error correction circuit while the second error correction circuit operates on the codeword.

12. The method of claim 11 , wherein the method includes stopping the iterative error correction with the first error correction circuit in response to the second error correction circuit reporting an uncorrectable error for the codeword.

13. The method of claim 10 , wherein the method includes:

correcting up to a threshold number of errors in the codeword with the second error correction circuit; and

reporting an uncorrectable error in response to the number of errors in the codeword exceeding the threshold.

14. The method of claim 13 , wherein the method includes:

using a quasi-cyclic low density parity check code to error correct the codeword with the first error correction circuit; and

using an algebraic code to error correct the codeword with the second error correction circuit.

15. A method, comprising:

receiving a codeword comprising hard data from a memory device;

iteratively error correcting the codeword on a layer-by-layer basis with a first error correction circuit until the codeword includes less than a threshold number of parity errors in a-particular layer, wherein a layer comprises a fraction of an iteration, and wherein the particular layer is a fraction other than a last fraction of a particular iteration;

error correcting the codeword with a second error correction circuit; and

receiving soft data from the memory device in response to failed error corrections by the first and the second error correction circuits.

16. The method of claim 15 , wherein the method includes transferring the codeword from the first error correction circuit to the second error correction circuit in response to the codeword including less than the threshold number of parity errors in the particular layer.

17. The method of claim 15 , wherein the method includes transferring the codeword from the second error correction circuit to a host in response to successful error corrections by the first and the second error correction circuits.

18. The method of claim 15 , wherein the method includes indicating a successful program verify operation in response to successful error corrections by the first and the second error correction circuits.

19. The method of claim 15 , wherein the method includes beginning error correcting the codeword with the second error correction circuit in response to stopping the iterative error correction with the first error correction circuit.

20. The method of claim 19 , wherein the method includes:

using a quasi-cyclic low density parity check code with the first error correction circuit; and

using an algebraic code with the second error correction circuit.

21. An apparatus, comprising:

an iterative error correction circuit configured to:

iteratively error correct a codeword on a layer-by-layer basis, wherein a layer comprises a fraction of an iteration;

update the codeword after each layer; and

transfer the codeword to an algebraic error correction circuit in response to a parity check being correct for a particular layer, wherein the particular layer is a fraction other than a last fraction of the particular iteration, and wherein the parity check being correct for the particular layer comprises the parity check resulting in less than a threshold number of parity errors.

22. The apparatus of claim 21 , wherein the iterative parity check is correct when there are no parity errors in the particular layer.

23. The apparatus of claim 21 , wherein the iterative parity check is correct when there are less than a threshold number of parity errors in the particular layer.

24. The apparatus of claim 23 , wherein the threshold number is selected based on a number of errors correctable by the algebraic error correction circuit.

25. The apparatus of claim 23 , wherein the apparatus is configured to select the threshold number based on a characteristic of the apparatus selected from the group of characteristics including: a temporal age of the apparatus, a number of program/erase cycles of the apparatus, a storage density of the apparatus, a retention rate of the apparatus, and a physical location within the apparatus where the codeword is stored.

26. The apparatus of claim 23 , wherein the threshold number of parity errors is a selectable option in firmware of the apparatus.

27. The apparatus of claim 21 , wherein the iterative error correction circuit comprises a quasi-cyclic low density parity check code circuit.

28. An apparatus, comprising:

a memory device;

a first correction circuit coupled to the memory device, wherein the first error correction circuit is configured to:

receive a codeword comprising hard data from the memory device; and

iteratively error correct the codeword on a layer-by-layer basis until the codeword includes less than a threshold number of parity errors in a particular layer of a particular iteration, wherein a layer comprises a fraction of an iteration, and wherein the particular layer is a fraction other than a last fraction of an iteration;

a second error correction circuit coupled to the first error correction circuit, wherein the second error correction circuit is configured to:

receive the codeword from the first error correction circuit after the codeword includes less than the threshold number of parity errors in the particular layer; and

error correct the codeword; and

a host interface coupled to the second error correction circuit, wherein the host interface is configured to receive the codeword in response to successful error correction by the second error correction circuit.

29. The apparatus of claim 28 , wherein the first error correction circuit is configured to receive soft data from the memory device in response to unsuccessful error correction by the second error correction circuit.

30. The apparatus of claim 28 , wherein the apparatus includes firmware that provides a selectable option to define the threshold number of parity errors.

31. The apparatus of claim 28 , wherein the first error correction circuit comprises a quasi-cyclic low density parity check (LDPC) code circuit and the second error correction circuit comprises an algebraic error correction circuit.

32. The apparatus of claim 31 , wherein the algebraic error correction circuit comprises one of the group including a Bose-Chaudhuri-Hocquenghem (BCH) error correction circuit, and a Reed Solomon error correction circuit.