Readout circuit for non-volatile memory device
View Patent ↗Provided is a readout circuit for a non-volatile memory device, which has a large readout margin for distinguishing between 0 and 1 of data and has a small circuit area. A voltage output from a single bias circuit is applied to a gate of a memory element and a gate of an NMOS transistor serving as a reference current source to be compared with a current flowing through the memory element. Thus, the gates are controlled by the same voltage, and hence characteristics fluctuations in the operating temperature range and the operating power supply voltage range are reduced. Therefore, a large readout margin for distinguishing 0 and 1 of data can be obtained, resulting in a simplified circuit configuration.
1. A readout circuit for an electrically rewritable non-volatile memory device, comprising:
a memory element including a source connected to a ground voltage, and a gate connected to one end of a first memory element selection switch controlled by a first memory element selection control signal;
a select gate transistor including a source connected to a drain of the memory element, and a gate controlled by a select gate selection control signal;
a second memory element selection switch including one end connected to a drain of the select gate transistor, and another end connected to an output of the readout circuit, the second memory element selection switch being controlled by a second memory element selection control signal;
a first NMOS transistor serving as a reference current source to be compared with a current flowing through the memory element;
a current mirror circuit comprising a first PMOS transistor and a second PMOS transistor, the first PMOS transistor including a gate and a drain which are connected to a drain of the first NMOS transistor, the second PMOS transistor including a gate connected to the gate of the first PMOS transistor and a drain connected to the output of the readout circuit; and
a first bias circuit including an output terminal connected to a gate of the first NMOS transistor and to another end of the first memory element selection switch.
2. A readout circuit for a non-volatile memory device according to claim 1 , further comprising:
a second NMOS transistor provided between the first NMOS transistor and the first PMOS transistor;
a third NMOS transistor provided between the second memory element selection switch and the output of the readout circuit; and
a second bias circuit for supplying a bias voltage to a gate of the second NMOS transistor and a gate of the third NMOS transistor.
3. A readout circuit for a non-volatile memory device according to claim 2 , further comprising a fourth NMOS transistor provided between the first NMOS transistor and the second NMOS transistor, the fourth NMOS transistor including a gate controlled by a dummy gate control signal.
4. A readout circuit for a non-volatile memory device according to claim 3 , wherein the fourth NMOS transistor comprises a transistor having the same characteristics as the select gate transistor.
5. A readout circuit for a non-volatile memory device according to claim 3 , further comprising:
a first dummy switch including one end connected to an output of the first bias circuit and another end connected to the gate of the first NMOS transistor, the first dummy switch being controlled by a first dummy switch control signal; and
a second dummy switch including one end connected to a source of the second NMOS transistor and another end connected to a drain of the fourth NMOS transistor, the second dummy switch being controlled by a second dummy switch control signal.
6. A readout circuit for a non-volatile memory device according to claim 5 , wherein:
the first memory element selection switch and the first dummy switch have the same characteristics; and
the second memory element selection switch and the second dummy switch have the same characteristics.
7. A readout circuit for a non-volatile memory device according to claim 4 , further comprising:
a first dummy switch including one end connected to an output of the first bias circuit and another end connected to the gate of the first NMOS transistor, the first dummy switch being controlled by a first dummy switch control signal; and
a second dummy switch including one end connected to a source of the second NMOS transistor and another end connected to a drain of the fourth NMOS transistor, the second dummy switch being controlled by a second dummy switch control signal.
8. A readout circuit for a non-volatile memory device according to claim 7 , wherein:
the first memory element selection switch and the first dummy switch have the same characteristics; and
the second memory element selection switch and the second dummy switch have the same characteristics.