Continuous time input stage
View Patent ↗A continuous time input stage including a first digital-to-analog converter (DAC) including a first DAC code input, a second DAC including a second DAC code input, a first set of switches coupled to the output of the first DAC, a second set of switches coupled to the output of the second DAC, and an amplifier configured to receive the output of either the first DAC or the second DAC.
1. A continuous time input stage, comprising:
a first digital-to-analog converter (DAC) including a first DAC code input;
a second DAC including a second DAC code input;
a first set of switches coupled to the output of the first DAC;
a second set of switches coupled to the output of the second DAC;
an amplifier configured, at input of the amplifier, to receive the output of either the first DAC or the second DAC based upon configuration of the first set of switches and the second set of switches; and
at least one integrator capacitor coupled between an output of the amplifier and the input of the amplifier.
2. The continuous time input stage of claim 1 , wherein the output of the first DAC is connected to the input of the amplifier based upon the configuration of the first set of switches.
3. The continuous time input stage of claim 1 , wherein the output of the second DAC is connected to the input of the amplifier based upon the configuration of the second set of switches.
4. The continuous time input stage of claim 1 , wherein the first DAC is configured to receive a new DAC code when the output of the second DAC is connected to the amplifier.
5. The continuous time input stage of claim 1 , wherein the second DAC is configured to receive a new DAC code when the output of the first DAC is connected to the amplifier.
6. The continuous time input stage of claim 1 , wherein the first set of switches are responsive to the state of a first clock and the second set of switches are responsive to the state of a second clock.
7. The continuous time input stage of claim 6 , wherein the first set of switches are configured to connect the output of the first DAC to the amplifier when the first clock is in a high state and the second clock is in a low state.
8. The continuous time input stage of claim 6 , wherein the second set of switches are configured to connect the output of the second DAC to the amplifier when the first clock is in a low state and the second clock is in a high state.
9. A continuous time input stage, comprising:
a first digital-to-analog converter (DAC) including a first DAC code input;
a second DAC including a second DAC code input;
a first pair of inputs, each coupled to an input resistor;
a second pair of inputs, each coupled to an input resistor;
a first set of switches coupled to the output of the first DAC;
a second set of switches coupled to the output of the second DAC; and
an amplifier configured, at input of the amplifier, to receive the output of either the first DAC or the second DAC based upon configuration of the first set of switches and the second set of switches; and
a third set of switches configured to connect an output of the amplifier with an integrator output of at least one integrator capacitor coupled between the output of the amplifier and the input of the amplifier.
10. The continuous time input stage of claim 9 , wherein the third set of switches is located between the output of the amplifier and the integrator output.
11. The continuous time input stage of claim 9 , wherein the third set of switches is located in the amplifier.
12. The continuous time input stage of claim 9 , wherein the output of the first DAC is connected to the input of the amplifier based upon the configuration of the first set of switches.
13. The continuous time input stage of claim 9 , wherein the output of the second DAC is connected to the input of the amplifier based upon the configuration of the second set of switches.
14. The continuous time input stage of claim 9 , wherein the first DAC is configured to receive a new DAC code when the output of the second DAC is connected to the amplifier.
15. The continuous time input stage of claim 9 , wherein the second DAC is configured to receive a new DAC code when the output of the first DAC is connected to the amplifier.
16. The continuous time input stage of claim 9 , wherein the first set of switches are responsive to the state of a first clock, the second set of switches are responsive to the state of a second clock, a first subset of the third set of switches is responsive to the state of the first clock, and a second subset of the third set of switches is responsive to the state of the second clock.
17. The continuous time input stage of claim 16 , wherein the first set of switches are configured to connect the output of the first DAC to the amplifier when the first clock is in a high state and the second clock is in a low state.
18. The continuous time input stage of claim 16 , wherein the second set of switches are configured to connect the output of the second DAC to the amplifier when the first clock is in a low state and the second clock is in a high state.
19. The continuous time input stage of claim 16 , wherein the third set of switches is configured to connect the output of the amplifier with the integrator output based upon the states of the first clock and the second clock.
20. A method for continuous time input, the method comprising:
determining that a first clock signal from a clock is in a high state;
activating a first set of switches based upon the determination that the first clock signal is in a high state;
receiving a new DAC code at a first DAC when the first set of switches are activated;
determining that a second clock signal from the clock is in a high state;
activating a second set of switches based upon the determination that the second clock signal is in a high state; and
receiving a new DAC code at a second DAC when the second set of switches are activated,
wherein an amplifier configured, at input of the amplifier, to receive the output of either the first DAC or the second DAC based upon configuration of the first set of switches and the second set of switches, and
at least one integrator capacitor coupled between output of the amplifier and the input of the amplifier, to generate integrated output.
21. The method of claim 20 , further comprising:
chopping an amplifier input and output using a third set of switches based upon a state of the third set of switches, the chopping occurring at a rate that is a multiple of a frequency of the clock.
22. The method of claim 20 , further comprising:
chopping an amplifier input and output using a third set of switches based upon a state of the third set of switches, the chopping occurring at a rate that is lower than a frequency of the clock.