INTERFACE BETWEEN A HOST AND A PERIPHERAL DEVICE
Disclosed are various embodiments for an interface between a host device and one or more peripheral devices in a computing system. A peripheral-side controller, a host-side controller, and a peripheral-side translator are located on a peripheral device that is in communication with a host device. The peripheral-side translator transfers data from an internal bus in the peripheral device to an external interface for the peripheral device. The internal bus is associated with a first bus protocol, and the external interface is associated with a second bus protocol.
1 . A system, comprising:
a host device comprising:
a bus fabric associated with a first bus protocol; and
a host-side translator in communication with the bus fabric, the host-side translator configured to provide data from the bus fabric to an external interface for the host device, the external interface being associated with a second bus protocol; and
a peripheral device comprising:
a peripheral-side translator in communication with the external interface, the peripheral-side translator configured to provide data from the external interface to an internal bus in the peripheral device, the internal bus being associated with a third bus protocol; and
a host-side controller configured to obtain data from the internal bus.
2 . The system of claim 1 , wherein the peripheral device further comprises a peripheral-side controller for the peripheral device, the peripheral-side controller being in communication with the host-side controller.
3 . The system of claim 1 , wherein:
the host-side translator is configured to convert the data from being in accordance with the first bus protocol to being in accordance with the second bus protocol; and
the peripheral-side translator is configured to convert the data from being in accordance with the second bus protocol to being in accordance with the third bus protocol.
4 . The system of claim 1 , wherein:
the host device comprises an additional host-side translator in communication with the bus fabric, the additional host-side translator configured to provide data to an additional external interface for the host device, the additional external interface being associated with the second bus protocol; and
the system comprises an additional peripheral device comprising:
an additional peripheral-side translator in communication with the additional external interface, the additional peripheral-side translator configured to provide data from the additional external interface to an additional internal bus in the additional peripheral device.
5 . The system of claim 4 , wherein the external interface comprises a pluralily of configurable lanes.
6 . The system of claim 1 , wherein the host device is located on a first chip and the peripheral device is located on a second chip.
7 . The system of claim 1 , wherein the first bus protocol and the third bus protocol are the same.
8 . The system of claim 1 , wherein the first bus protocol and the third bus protocol are different.
9 . The system of claim 1 , wherein the second bus protocol is based at least in part on a MIPI Low Latency Interface (LLI) protocol, a Peripheral Component Interconnect (PCI) protocol, or any combination thereof.
10 . A method, comprising:
transferring, using a host device, data from a bus fabric in the host device to an external interface for the host device, the bus fabric being associated with a first bus protocol, the external interface being associated with a second bus protocol;
transferring, using a peripheral device, data from the external interface to an internal bus for the peripheral device, the internal bus being associated with a third bus protocol; and
transferring, in the peripheral device, data from the internal bus to a host-side controller that is located in the peripheral device.
11 . The method of claim 10 , further comprising translating, in the host device, data from being in accordance with the first bus protocol to being in accordance with the second bus protocol.
12 . The method of claim 10 , further comprising translating, in the peripheral device, data from being in accordance with the second bus protocol to being in accordance with the third bus protocol.
13 . The method of claim 10 , further comprising communicating with the host-side controller using a peripheral-side controller that is located in the peripheral device.
14 . The method of claim 10 , wherein the first bus protocol and the third bus protocol are different from the second bus protocol.
15 . The method of claim 10 , wherein the second bus protocol is based at least in part on a MIPI Low Latency Interface (LLI) bus protocol.
16 . The method of claim 10 , wherein the second bus protocol is based at least in part on a Peripheral Component Interconnect (PCI) bus protocol
17 . An apparatus, comprising:
a peripheral-side controller;
a host-side controller in communication with the peripheral-side controller;
an internal bus in communication with the host-side controller, the internal bus being associated with a first bus protocol; and
a peripheral-side translator configured to transfer data from the internal bus to an external interface, the external interface being associated with a second bus protocol.
18 . The apparatus of claim 17 , wherein the peripheral-side controller and the host-side controller are on a same chip.
19 . The apparatus of claim 17 , wherein the second bus protocol is based at least in part on a MIPI Low Latency Interface (LLD.
20 . The apparatus of claim 17 , wherein the second bus protocol is based at least in part on a MIPI Low Latency Interface (LLI) or a Peripheral Component Interconnect (PCI) protocol