Segmented digital-to-analog converter having weighted current sources
View Patent ↗A digital input to a digital-to-analog converter (DAC) is divided into a most significant portion and a lesser significant portion. At least one tap voltage generator generates a plurality of voltages, preferably using a resistor string. A decoder decodes at least one sub-word that forms the lesser significant portion to generate a corresponding at least one control signal. A switching unit accesses voltages generated by the at least one tap voltage generator in response to the at least one control signal. A scaled current generator generates a respective weighted current from each accessed voltage. An output stage combines all the weighted currents with a voltage that is an analog representation of the most significant portion of the digital input to generate an analog approximation of the entire digital input.
1. A digital-to-analog converter (DAC), comprising:
a circuit that receives a digital input;
a circuit that generates at least one weighted current in response to the digital input, wherein the at least one weighted current includes a plurality of weighted currents; and
an output stage that combines a first voltage with the plurality of weighted currents to generate an output signal that is an analog approximation of the digital input.
2. The DAC of claim 1 , wherein the DAC divides the digital input into a plurality of sub-words and generates the first voltage as an analog approximation of a most significant one of the sub-words.
3. The DAC of claim 2 , wherein each current is generated based on a respective one of the remaining sub-words.
4. The DAC of claim 3 , wherein:
currents generated based on less significant sub-words are assigned lower weights compared to currents generated based on more significant sub-words.
5. A digital-to-analog converter (DAC), comprising:
a circuit that receives a digital input;
a circuit that generates at least one weighted current in response to the digital input; and
an output stage that combines a first voltage with at least one weighted current to generate an output signal that is an analog approximation of the digital input,
wherein:
the DAC divides the digital input into a plurality of sub-words and generates the first voltage as an analog approximation of a most significant one of the sub-words;
each current is generated based on a respective one of the remaining sub-words;
the at least one weighted current includes a plurality of currents;
the output stage includes an operational amplifier in non-inverting configuration with a feedback formed by a resistor string connected between the output signal and ground; and
each current is connected to a respective node in the resistor string.
6. The DAC of claim 5 , wherein currents generated based on less significant sub-words are connected to nodes that are located closer to ground compared to currents generated based on more significant sub-words.
7. The DAC of claim 1 , wherein each current is produced by a respective operational amplifier that drives a transistor.
8. A digital-to-analog converter (DAC), comprising:
a circuit that receives a digital input;
a circuit that generates at least one weighted current in response to the digital input;
an output stage that combines a first voltage with at least one weighted current to generate an output signal that is an analog approximation of the digital input,
wherein each current is produced by a respective operational amplifier that drives a transistor; and
a respective resistor connecting a source terminal of each transistor to at least one reference voltage.
9. The DAC of claim 8 , wherein the at least one reference voltage is connected to each resistor through a buffer.
10. The DAC of claim 8 , wherein:
each operational amplifier is configured in non-inverting mode with an inverting input of the operational amplifier connected to the source terminal of each transistor; and
a voltage selected as a function of a respective sub-word is applied to a non-inverting input of each operational amplifier.
11. The DAC of claim 10 , further comprising a decoder that connects each selected voltage to a respective operational amplifier in response to decoding the sub-words.
12. The DAC of claim 10 , further comprising:
a tap voltage generator outputting each selected voltage; and
a switching unit that switchably connects each selected voltage to the non-inverting input of a respective operational amplifier.
13. The DAC of claim 1 , wherein the DAC is configured so that the currents are non-zero for all possible values of the digital input.
14. The DAC of claim 1 , wherein the output signal is a substantially monotonic function of the digital input.
15. A scaled current generator, comprising:
at least one current source that outputs a weighted current corresponding to a respective lesser significant sub-word of a digital input of a digital-to-analog converter (DAC) in which the digital input is divided into a most significant sub-word and at least one lesser significant sub-word,
wherein:
each current is produced by a respective operational amplifier that drives a transistor and that is configured in non-inverting mode with an inverting input of the operational amplifier connected to a source terminal of the transistor and to a resistor connected to a reference voltage; and
a voltage selected as a function of a respective sub-word is applied to a non-inverting input of each operational amplifier.
16. The scaled current generator of claim 15 , wherein:
the digital input is divided into a plurality of lesser significant sub-words; and
currents generated based on less significant sub-words are assigned lower weights compared to currents generated based on more significant sub-words.
17. The scaled current generator of claim 15 , wherein the currents are non-zero for all possible values of the digital input.
18. A digital-to-analog converter (DAC), comprising:
at least one tap voltage generator that generates a plurality of voltages;
a decoder that decodes at least one sub-word that forms a lesser significant portion of a digital input of the DAC to generate a corresponding at least one control signal, wherein the digital input is divided by the DAC into a most significant portion and the lesser significant portion;
a switching unit that accesses a plurality of voltages generated by the at least one tap voltage generator in response to the at least one control signal;
a scaled current generator that generates a respective weighted current from each accessed voltage; and
an output stage that combines all the weighted currents with a voltage that is an analog representation of the most significant portion of the digital input to generate an analog approximation of the entire digital input.
19. A digital-to-analog converter (DAC), comprising:
a plurality of sub-DACs, each of which processes a respective portion of a digital input, outputs of the sub-DACs being combined to generate an output signal that is an analog approximation of the digital input;
wherein at least one of the sub-DACs includes an output stage that combines a first voltage with a plurality of weighted currents to generate, as the output of the sub-DAC, a voltage that is an analog approximation of the respective portion of the digital input.
20. The DAC of claim 2 , wherein the plurality of sub-words provide at least three levels of segmentation for the digital input.
21. The DAC of claim 3 , wherein each current is combined with the first voltage through injection at a different point in a resistor string.