Semiconductor device having timing control for read-write memory access operations
A semiconductor device avoids the disturb problem and the collision between write and read operations in a DP-SRAM cell or a 2P-SRAM cell. The semiconductor device 1 includes a write word line WLA and a read word line WLB each coupled to memory cells 3 . A read operation activates the read word line WLB corresponding to the selected memory cell 3 . A write operation activates the write word line WLA corresponding to the selected memory cell 3 . The selected write word line WLA is activated after activation of the selected read word line WLB in an operation cycle that performs both read and write operations.
1. A semiconductor device comprising:
a plurality of first word lines;
a plurality of second word lines;
a plurality of memory cells, each memory cell being coupled to a corresponding one of the first word lines and a corresponding one of the second word lines, said each memory cell becoming accessible when at least one of the corresponding first word line and the corresponding second word line is activated; and
a first word line selection circuit that activates a selected one of the first word lines during a read operation; and
a second word line selection circuit that activates a selected one of the second word lines during a write operation,
wherein the selected second word line is activated after the selected first word line is activated, in a single operation cycle performing both the read operation and the write operation.
2. The semiconductor device according to claim 1 , further comprising:
a sense amplifier that receives data stored in a memory cell coupled to the selected first word line,
wherein the selected second word line is activated no earlier than when the sense amplifier is activated.
3. The semiconductor device according to claim 1 ,
wherein the selected second word line is activated before the selected first word line is deactivated.
4. The semiconductor device according to claim 1 , further comprising:
a plurality of bit lines; and
a drive circuit;
wherein each memory cell is coupled to a corresponding one of the bit lines;
wherein the drive circuit drives a selected one of the plurality of bit lines during a write operation, and
wherein the drive circuit is configured to drive the selected bit line before the selected second word line is activated.
5. The semiconductor device according to claim 4 , further comprising:
a sense amplifier that receives data stored in a memory cell coupled to the selected first word line,
wherein the drive circuit is configured to drive the selected bit line before the sense amplifier is activated.
6. The semiconductor device according to claim 1 , further comprising:
a timing generation circuit configured to generate a first timing control signal to activate the selected first word line and also generate a second timing control signal to activate the selected second word line,
wherein the timing generation circuit includes a delay circuit that delays the first timing control signal to generate a delay signal; and
wherein the second timing control signal is generated from the delay signal.
7. The semiconductor device according to claim 6 , further comprising:
a sense amplifier that receives data stored in a memory cell coupled to the selected first word line,
wherein the timing generation circuit generates a third timing control signal from the delay signal, the third timing control signal being configured to activate the sense amplifier, and
wherein the third timing control signal is configured to activate the sense amplifier no later than when selected second word line is activated by the second timing control signal.
8. The semiconductor device according to claim 6 , further comprising:
a plurality of bit lines; and
a drive circuit,
wherein the memory cells are each coupled to a corresponding one of the bit lines,
wherein the drive circuit drives a selected one of the plurality of bit lines during a write operation;
wherein the timing generation circuit generates a fourth timing control signal from the first timing control signal, the fourth timing control signal being configured to activate the drive circuit to drive the selected bit line; and
wherein the fourth timing control signal is configured to activate the drive circuit to drive the selected bit line before the selected second word line is activated by the second timing control signal.
9. The semiconductor device according to claim 1 ,
wherein tR denotes a period during which the selected first word line is activated, and
the selected second word line is activated after time tR/2 has elapsed from when the selected first word line is activated.